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arm: nxp: kl2x: Move to using UART_MCUX_LPSCI for UART0

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Cleanup soc code to enable UART_MCUX_LPSCI to support UART0.

Change-Id: I173febffcffc902f228946124e0434f122a67607
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2017-04-26 10:08:23 -05:00
commit 62d2d362ac
3 changed files with 6 additions and 3 deletions
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2
arch/arm/soc/nxp_kinetis/kl2x/Kconfig.defconfig.mkl25z4
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@ -31,7 +31,7 @@ endif # GPIO
if SERIAL if SERIAL
config UART_MCUX config UART_MCUX_LPSCI
def_bool y def_bool y
endif # SERIAL endif # SERIAL

1
arch/arm/soc/nxp_kinetis/kl2x/Kconfig.soc
View file

@ -15,6 +15,7 @@ config SOC_MKL25Z4
select HAS_MCUX select HAS_MCUX
select HAS_OSC select HAS_OSC
select HAS_MCG select HAS_MCG
select HAS_LPSCI
endchoice endchoice

6
arch/arm/soc/nxp_kinetis/kl2x/soc.c
View file

@ -13,6 +13,8 @@
#include <fsl_clock.h> #include <fsl_clock.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#define LPSCI0SRC_MCGFLLCLK (1)
/******************************************************************************* /*******************************************************************************
* Variables * Variables
******************************************************************************/ ******************************************************************************/
@ -93,8 +95,8 @@ static ALWAYS_INLINE void clkInit(void)
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0); CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
CLOCK_SetSimConfig(&simConfig); CLOCK_SetSimConfig(&simConfig);
#ifdef CONFIG_UART_MCUX_0 #ifdef CONFIG_UART_MCUX_LPSCI_0
CLOCK_SetLpsci0Clock(1); CLOCK_SetLpsci0Clock(LPSCI0SRC_MCGFLLCLK);
#endif #endif
} }