drivers: ethernet: mii: provide bit val
Provide bit value for control registers to be able to use WRITE_BIT() macro. Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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1 changed files with 47 additions and 26 deletions
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@ -54,32 +54,41 @@
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#define MII_ESTAT 0xf
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/* Basic Mode Control Register (BMCR) bit definitions */
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#define MII_BMCR_RESET_BIT 15
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#define MII_BMCR_LOOPBACK_BIT 14
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#define MII_BMCR_SPEED_LSB_BIT 13
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#define MII_BMCR_AUTONEG_ENABLE_BIT 12
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#define MII_BMCR_POWER_DOWN_BIT 11
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#define MII_BMCR_ISOLATE_BIT 10
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#define MII_BMCR_AUTONEG_RESTART_BIT 9
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#define MII_BMCR_DUPLEX_MODE_BIT 8
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#define MII_BMCR_SPEED_MSB_BIT 6
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/** PHY reset */
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#define MII_BMCR_RESET BIT(15)
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#define MII_BMCR_RESET BIT(MII_BMCR_RESET_BIT)
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/** enable loopback mode */
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#define MII_BMCR_LOOPBACK BIT(14)
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#define MII_BMCR_LOOPBACK BIT(MII_BMCR_LOOPBACK_BIT)
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/** 10=1000Mbps 01=100Mbps; 00=10Mbps */
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#define MII_BMCR_SPEED_LSB BIT(13)
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#define MII_BMCR_SPEED_LSB BIT(MII_BMCR_SPEED_LSB_BIT)
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/** Auto-Negotiation enable */
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#define MII_BMCR_AUTONEG_ENABLE BIT(12)
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#define MII_BMCR_AUTONEG_ENABLE BIT(MII_BMCR_AUTONEG_ENABLE_BIT)
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/** power down mode */
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#define MII_BMCR_POWER_DOWN BIT(11)
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#define MII_BMCR_POWER_DOWN BIT(MII_BMCR_POWER_DOWN_BIT)
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/** isolate electrically PHY from MII */
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#define MII_BMCR_ISOLATE BIT(10)
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#define MII_BMCR_ISOLATE BIT(MII_BMCR_ISOLATE_BIT)
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/** restart auto-negotiation */
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#define MII_BMCR_AUTONEG_RESTART BIT(9)
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#define MII_BMCR_AUTONEG_RESTART BIT(MII_BMCR_AUTONEG_RESTART_BIT)
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/** full duplex mode */
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#define MII_BMCR_DUPLEX_MODE BIT(8)
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#define MII_BMCR_DUPLEX_MODE BIT(MII_BMCR_DUPLEX_MODE_BIT)
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/** 10=1000Mbps 01=100Mbps; 00=10Mbps */
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#define MII_BMCR_SPEED_MSB BIT(6)
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#define MII_BMCR_SPEED_MSB BIT(MII_BMCR_SPEED_MSB_BIT)
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/** Link Speed Field */
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#define MII_BMCR_SPEED_MASK (BIT(6) | BIT(13))
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#define MII_BMCR_SPEED_MASK (MII_BMCR_SPEED_MSB | MII_BMCR_SPEED_LSB)
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/** select speed 10 Mb/s */
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#define MII_BMCR_SPEED_10 0
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#define MII_BMCR_SPEED_10 0
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/** select speed 100 Mb/s */
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#define MII_BMCR_SPEED_100 BIT(13)
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#define MII_BMCR_SPEED_100 BIT(MII_BMCR_SPEED_LSB_BIT)
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/** select speed 1000 Mb/s */
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#define MII_BMCR_SPEED_1000 BIT(6)
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#define MII_BMCR_SPEED_1000 BIT(MII_BMCR_SPEED_MSB_BIT)
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/* Basic Mode Status Register (BMSR) bit definitions */
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/** 100BASE-T4 capable */
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@ -115,36 +124,48 @@
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/* Auto-negotiation Advertisement Register (ANAR) bit definitions */
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/* Auto-negotiation Link Partner Ability Register (ANLPAR) bit definitions */
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#define MII_ADVERTISE_NEXT_PAGE_BIT 15
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#define MII_ADVERTISE_LPACK_BIT 14
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#define MII_ADVERTISE_REMOTE_FAULT_BIT 13
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#define MII_ADVERTISE_ASYM_PAUSE_BIT 11
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#define MII_ADVERTISE_PAUSE_BIT 10
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#define MII_ADVERTISE_100BASE_T4_BIT 9
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#define MII_ADVERTISE_100_FULL_BIT 8
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#define MII_ADVERTISE_100_HALF_BIT 7
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#define MII_ADVERTISE_10_FULL_BIT 6
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#define MII_ADVERTISE_10_HALF_BIT 5
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/** next page */
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#define MII_ADVERTISE_NEXT_PAGE BIT(15)
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#define MII_ADVERTISE_NEXT_PAGE BIT(MII_ADVERTISE_NEXT_PAGE_BIT)
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/** link partner acknowledge response */
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#define MII_ADVERTISE_LPACK BIT(14)
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#define MII_ADVERTISE_LPACK BIT(MII_ADVERTISE_LPACK_BIT)
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/** remote fault */
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#define MII_ADVERTISE_REMOTE_FAULT BIT(13)
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#define MII_ADVERTISE_REMOTE_FAULT BIT(MII_ADVERTISE_REMOTE_FAULT_BIT)
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/** try for asymmetric pause */
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#define MII_ADVERTISE_ASYM_PAUSE BIT(11)
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#define MII_ADVERTISE_ASYM_PAUSE BIT(MII_ADVERTISE_ASYM_PAUSE_BIT)
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/** try for pause */
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#define MII_ADVERTISE_PAUSE BIT(10)
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#define MII_ADVERTISE_PAUSE BIT(MII_ADVERTISE_PAUSE_BIT)
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/** try for 100BASE-T4 support */
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#define MII_ADVERTISE_100BASE_T4 BIT(9)
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#define MII_ADVERTISE_100BASE_T4 BIT(MII_ADVERTISE_100BASE_T4_BIT)
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/** try for 100BASE-X full duplex support */
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#define MII_ADVERTISE_100_FULL BIT(8)
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#define MII_ADVERTISE_100_FULL BIT(MII_ADVERTISE_100_FULL_BIT)
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/** try for 100BASE-X support */
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#define MII_ADVERTISE_100_HALF BIT(7)
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#define MII_ADVERTISE_100_HALF BIT(MII_ADVERTISE_100_HALF_BIT)
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/** try for 10 Mb/s full duplex support */
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#define MII_ADVERTISE_10_FULL BIT(6)
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#define MII_ADVERTISE_10_FULL BIT(MII_ADVERTISE_10_FULL_BIT)
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/** try for 10 Mb/s half duplex support */
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#define MII_ADVERTISE_10_HALF BIT(5)
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#define MII_ADVERTISE_10_HALF BIT(MII_ADVERTISE_10_HALF_BIT)
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/** Selector Field Mask */
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#define MII_ADVERTISE_SEL_MASK (0x1F << 0)
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#define MII_ADVERTISE_SEL_MASK (0x1F << 0)
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/** Selector Field */
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#define MII_ADVERTISE_SEL_IEEE_802_3 0x01
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/* 1000BASE-T Control Register bit definitions */
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#define MII_ADVERTISE_1000_FULL_BIT 9
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#define MII_ADVERTISE_1000_HALF_BIT 8
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/** try for 1000BASE-T full duplex support */
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#define MII_ADVERTISE_1000_FULL BIT(9)
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#define MII_ADVERTISE_1000_FULL BIT(MII_ADVERTISE_1000_FULL_BIT)
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/** try for 1000BASE-T half duplex support */
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#define MII_ADVERTISE_1000_HALF BIT(8)
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#define MII_ADVERTISE_1000_HALF BIT(MII_ADVERTISE_1000_HALF_BIT)
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/** Advertise all speeds */
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#define MII_ADVERTISE_ALL (MII_ADVERTISE_10_HALF | MII_ADVERTISE_10_FULL |\
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