diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt
index edae619f2d8..536fc52adeb 100644
--- a/drivers/clock_control/CMakeLists.txt
+++ b/drivers/clock_control/CMakeLists.txt
@@ -22,6 +22,7 @@ else()
   zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F3X clock_stm32f0_f3.c)
   zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F4X clock_stm32f2_f4_f7.c)
   zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F7X clock_stm32f2_f4_f7.c)
+  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32G0X clock_stm32g0.c)
   zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L0X clock_stm32l0_l1.c)
   zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L1X clock_stm32l0_l1.c)
   zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X clock_stm32l4_wb.c)
diff --git a/drivers/clock_control/Kconfig.stm32 b/drivers/clock_control/Kconfig.stm32
index 29218783185..e40150dc334 100644
--- a/drivers/clock_control/Kconfig.stm32
+++ b/drivers/clock_control/Kconfig.stm32
@@ -125,7 +125,7 @@ source "drivers/clock_control/Kconfig.stm32f2_f4_f7"
 source "drivers/clock_control/Kconfig.stm32h7"
 source "drivers/clock_control/Kconfig.stm32l0_l1"
 source "drivers/clock_control/Kconfig.stm32l4_wb"
-
+source "drivers/clock_control/Kconfig.stm32g0"
 
 # Bus clocks configuration options
 
diff --git a/drivers/clock_control/Kconfig.stm32g0 b/drivers/clock_control/Kconfig.stm32g0
new file mode 100644
index 00000000000..0b500a181b3
--- /dev/null
+++ b/drivers/clock_control/Kconfig.stm32g0
@@ -0,0 +1,51 @@
+# Kconfig - STM32G0 PLL configuration options
+#
+# Copyright (c) 2019 Linaro
+#
+#  SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_SERIES_STM32G0X
+
+config CLOCK_STM32_PLL_N_MULTIPLIER
+	int "PLL multiplier"
+	depends on CLOCK_STM32_SYSCLK_SRC_PLL
+	default 8
+	range 8 86
+	help
+	 PLL multiplier, allowed values: 8-86
+	 PLL output must not exceed 56MHz(1.8V)/26MHz(1.2V).
+
+config CLOCK_STM32_PLL_M_DIVISOR
+	int "PLL divisor"
+	depends on CLOCK_STM32_SYSCLK_SRC_PLL
+	default 1
+	range 1 8
+	help
+	  PLL divisor, allowed values: 1-8.
+
+config CLOCK_STM32_PLL_P_DIVISOR
+	int "PLL P Divisor"
+	depends on CLOCK_STM32_SYSCLK_SRC_PLL
+	default 2
+	range 2 32
+	help
+	  PLL P VCO divisor, allowed values: 2-32.
+
+config CLOCK_STM32_PLL_Q_DIVISOR
+	int "PLL Q Divisor"
+	depends on CLOCK_STM32_SYSCLK_SRC_PLL
+	default 2
+	range 2 8
+	help
+	  PLL Q VCO divisor, allowed values: 2-8.
+
+config CLOCK_STM32_PLL_R_DIVISOR
+	int "PLL R Divisor"
+	depends on CLOCK_STM32_SYSCLK_SRC_PLL
+	default 2
+	range 2 8
+	help
+	  PLL R VCO divisor, allowed values: 2-8.
+
+endif # SOC_SERIES_STM32G0X
diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c
index eecf6f9b698..5f143cb4c8f 100644
--- a/drivers/clock_control/clock_stm32_ll_common.c
+++ b/drivers/clock_control/clock_stm32_ll_common.c
@@ -54,10 +54,10 @@ static void config_bus_clk_init(LL_UTILS_ClkInitTypeDef *clk_init)
 	clk_init->APB1CLKDivider = apb1_prescaler(
 					CONFIG_CLOCK_STM32_APB1_PRESCALER);
 
-#ifndef CONFIG_SOC_SERIES_STM32F0X
+#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
 	clk_init->APB2CLKDivider = apb2_prescaler(
 					CONFIG_CLOCK_STM32_APB2_PRESCALER);
-#endif /* CONFIG_SOC_SERIES_STM32F0X  */
+#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
 }
 
 static u32_t get_bus_clock(u32_t clock, u32_t prescaler)
@@ -96,16 +96,16 @@ static inline int stm32_clock_control_on(struct device *dev,
 		LL_APB1_GRP2_EnableClock(pclken->enr);
 		break;
 #endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X */
-#ifndef CONFIG_SOC_SERIES_STM32F0X
+#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
 	case STM32_CLOCK_BUS_APB2:
 		LL_APB2_GRP1_EnableClock(pclken->enr);
 		break;
-#endif /* CONFIG_SOC_SERIES_STM32F0X */
-#ifdef CONFIG_SOC_SERIES_STM32L0X
+#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
+#if defined (CONFIG_SOC_SERIES_STM32L0X) || defined (CONFIG_SOC_SERIES_STM32G0X)
 	case STM32_CLOCK_BUS_IOP:
 		LL_IOP_GRP1_EnableClock(pclken->enr);
 		break;
-#endif /* CONFIG_SOC_SERIES_STM32L0X */
+#endif /* CONFIG_SOC_SERIES_STM32L0X || CONFIG_SOC_SERIES_STM32G0X */
 	default:
 		return -ENOTSUP;
 	}
@@ -144,11 +144,11 @@ static inline int stm32_clock_control_off(struct device *dev,
 		LL_APB1_GRP2_DisableClock(pclken->enr);
 		break;
 #endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X */
-#ifndef CONFIG_SOC_SERIES_STM32F0X
+#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
 	case STM32_CLOCK_BUS_APB2:
 		LL_APB2_GRP1_DisableClock(pclken->enr);
 		break;
-#endif /* CONFIG_SOC_SERIES_STM32F0X */
+#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
 #ifdef CONFIG_SOC_SERIES_STM32L0X
 	case STM32_CLOCK_BUS_IOP:
 		LL_IOP_GRP1_DisableClock(pclken->enr);
@@ -176,10 +176,10 @@ static int stm32_clock_control_get_subsys_rate(struct device *clock,
 	u32_t ahb_clock = SystemCoreClock;
 	u32_t apb1_clock = get_bus_clock(ahb_clock,
 				CONFIG_CLOCK_STM32_APB1_PRESCALER);
-#ifndef CONFIG_SOC_SERIES_STM32F0X
+#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
 	u32_t apb2_clock = get_bus_clock(ahb_clock,
 				CONFIG_CLOCK_STM32_APB2_PRESCALER);
-#endif /* CONFIG_SOC_SERIES_STM32F0X */
+#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
 
 	ARG_UNUSED(clock);
 
@@ -199,11 +199,11 @@ static int stm32_clock_control_get_subsys_rate(struct device *clock,
 #endif
 		*rate = apb1_clock;
 		break;
-#ifndef CONFIG_SOC_SERIES_STM32F0X
+#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
 	case STM32_CLOCK_BUS_APB2:
 		*rate = apb2_clock;
 		break;
-#endif /* CONFIG_SOC_SERIES_STM32F0X */
+#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
 	default:
 		return -ENOTSUP;
 	}
@@ -376,9 +376,9 @@ static int stm32_clock_control_init(struct device *dev)
 
 	/* Set APB1 & APB2 prescaler*/
 	LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider);
-#ifndef CONFIG_SOC_SERIES_STM32F0X
+#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
 	LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider);
-#endif /* CONFIG_SOC_SERIES_STM32F0X */
+#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
 
 	/* Set flash latency */
 	/* HSI used as SYSCLK, set latency to 0 */
@@ -447,9 +447,9 @@ static int stm32_clock_control_init(struct device *dev)
 
 	/* Set APB1 & APB2 prescaler*/
 	LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider);
-#ifndef CONFIG_SOC_SERIES_STM32F0X
+#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
 	LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider);
-#endif /* CONFIG_SOC_SERIES_STM32F0X */
+#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
 
 	/* Set flash latency */
 	/* HSI used as SYSCLK, set latency to 0 */
diff --git a/drivers/clock_control/clock_stm32g0.c b/drivers/clock_control/clock_stm32g0.c
new file mode 100644
index 00000000000..8ea7bc81cf1
--- /dev/null
+++ b/drivers/clock_control/clock_stm32g0.c
@@ -0,0 +1,51 @@
+/*
+ *
+ * Copyright (c) 2019 Ilya Tagunov
+ * Copyright (c) 2019 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <soc.h>
+#include <clock_control.h>
+#include <misc/util.h>
+#include <clock_control/stm32_clock_control.h>
+#include "clock_stm32_ll_common.h"
+
+
+#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
+
+/* Macros to fill up multiplication and division factors values */
+#define z_pll_div(v) LL_RCC_PLLM_DIV_ ## v
+#define pll_div(v) z_pll_div(v)
+
+#define z_pllr(v) LL_RCC_PLLR_DIV_ ## v
+#define pllr(v) z_pllr(v)
+
+/**
+ * @brief Fill PLL configuration structure
+ */
+void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
+{
+	pllinit->PLLN = CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER;
+	pllinit->PLLM = pll_div(CONFIG_CLOCK_STM32_PLL_M_DIVISOR);
+	pllinit->PLLR = pllr(CONFIG_CLOCK_STM32_PLL_R_DIVISOR);
+}
+#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
+
+/**
+ * @brief Activate default clocks
+ */
+void config_enable_default_clocks(void)
+{
+	/* Do nothing */
+}
+
+/**
+ * @brief Function kept for driver genericity
+ */
+void LL_RCC_MSI_Disable(void)
+{
+	/* Do nothing */
+}
diff --git a/dts/arm/st/g0/stm32g0.dtsi b/dts/arm/st/g0/stm32g0.dtsi
index 3236f3a7225..a4ca246c8a4 100644
--- a/dts/arm/st/g0/stm32g0.dtsi
+++ b/dts/arm/st/g0/stm32g0.dtsi
@@ -46,9 +46,17 @@
 			};
 		};
 
+		rcc: rcc@40021000 {
+			compatible = "st,stm32-rcc";
+			clocks-controller;
+			#clock-cells = <2>;
+			reg = <0x40021000 0x400>;
+			label = "STM32_CLK_RCC";
+		};
+
 	};
 };
 
 &nvic {
 	arm,num-irq-priority-bits = <2>;
-};
\ No newline at end of file
+};