board/nsim: Add support of ARC HS cores in nSIM

ARC nSIM simulates pretty much any modern ARC core,
moreover it emulates a lot of different core features so
it is possible to play with them even wo real hardware.

Thus we add yet another ARC core family to be used on simulated
nSIM board.

For now it's just a basic configuration with ARC UART for
smoke-testing of Zephyr on ARC HS CPUs.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

boards/arc/nsim/board.cmake

@@ -9,6 +9,8 @@ if(${CONFIG_SOC_NSIM_EM})
 board_runner_args(arc-nsim "--props=nsim_em.props")
 elseif(${CONFIG_SOC_NSIM_SEM})
 board_runner_args(arc-nsim "--props=nsim_sem.props")
+elseif(${CONFIG_SOC_NSIM_HS})
+board_runner_args(arc-nsim "--props=nsim_hs.props")
 endif()
 
 board_finalize_runner_args(arc-nsim)

boards/arc/nsim/doc/index.rst

@@ -1,4 +1,4 @@
-.. _nsim_em:
+.. _nsim:
 
 DesignWare(R) ARC(R) Emulation (nsim)
 #####################################
@@ -7,20 +7,22 @@ Overview
 ********
 
 This board configuration will use `Designware ARC nSIM`_ to emulate a virtual
-ARC EM based board including the following features:
+ARC EM or ARC HS based board including the following features:
 
-* ARC EM processor
+* ARC EM or ARC HS processor
 * ARC internal timer
 * a virtual output only console (uart-nsim)
 
-There are two sub configurations in board:
+There are three supported board sub-configurations:
 
-* nsim_em which includes normal em features and ARC MPUv2
-* nsim_sem which includes secure em features and ARC MPUv3
+* ``nsim_em`` which includes normal ARC EM features and ARC MPUv2
+* ``nsim_sem`` which includes secure ARC EM features and ARC MPUv3
+* ``nsim_hs`` which includes base ARC HS features, i.e. w/o PMU and MMU
 
 For detailed arc features, please refer to
-:zephyr_file:`boards/arc/nsim/support/nsim_em.props` and
-:zephyr_file:`boards/arc/nsim/support/nsim_sem.props`.
+:zephyr_file:`boards/arc/nsim/support/nsim_em.props`,
+:zephyr_file:`boards/arc/nsim/support/nsim_sem.props` and
+:zephyr_file:`boards/arc/nsim/support/nsim_hs.props`.
 
 
 Hardware
@@ -30,15 +32,15 @@ Supported Features
 
 The following hardware features are supported:
 
-+-----------+------------+-----+-------+-----------------------+
-| Interface | Controller | EM  | SEM   | Driver/Component      |
-+===========+============+=====+=======+=======================+
-| INT       | on-chip    | Y   | Y     | interrupt_controller  |
-+-----------+------------+-----+-------+-----------------------+
-| UART      | nsim uart  | Y   | Y     | serial port-polling   |
-+-----------+------------+-----+-------+-----------------------+
-| TIMER     | on-chip    | Y   | Y     | system clock          |
-+-----------+------------+-----+-------+-----------------------+
++-----------+------------+-----+-------+-----+-----------------------+
+| Interface | Controller | EM  | SEM   | HS  | Driver/Component      |
++===========+============+=====+=======+=====+=======================+
+| INT       | on-chip    | Y   | Y     | Y   | interrupt_controller  |
++-----------+------------+-----+-------+-----+-----------------------+
+| UART      | nsim uart  | Y   | Y     | Y   | serial port-polling   |
++-----------+------------+-----+-------+-----+-----------------------+
+| TIMER     | on-chip    | Y   | Y     | Y   | system clock          |
++-----------+------------+-----+-------+-----+-----------------------+
 
 
 Programming and Debugging

boards/arc/nsim/nsim_hs.dts

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019, Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "nsim.dtsi"
+
+/ {
+	model = "snps,nsim_hs";
+	compatible = "snps,nsim_hs";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "snps,archs";
+			reg = <0>;
+		};
+	};
+};

boards/arc/nsim/nsim_hs.yaml

@@ -0,0 +1,11 @@
+identifier: nsim_hs
+name: HS nSIM simulator
+type: mcu
+simulation: nsim
+arch: arc
+toolchain:
+  - zephyr
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/arc/nsim/nsim_hs_defconfig

@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARC=y
+CONFIG_CPU_ARCHS=y
+CONFIG_SOC_NSIM=y
+CONFIG_SOC_NSIM_HS=y
+CONFIG_BOARD_NSIM=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
+CONFIG_XIP=n
+CONFIG_BUILD_OUTPUT_BIN=n
+CONFIG_PRINTK=y
+CONFIG_ARCV2_INTERRUPT_UNIT=y
+CONFIG_ARCV2_TIMER=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_ARC_EXCEPTION_DEBUG=y

boards/arc/nsim/support/nsim_hs.props

@@ -0,0 +1,46 @@
+	nsim_isa_family=av2hs
+	nsim_isa_core=2
+	arcver=0x52
+	nsim_isa_rgf_num_banks=2
+	nsim_isa_rgf_banked_regs=32
+	nsim_isa_rgf_num_regs=32
+	nsim_isa_rgf_num_wr_ports=2
+	nsim_isa_big_endian=0
+	nsim_isa_lpc_size=32
+	nsim_isa_pc_size=32
+	nsim_isa_addr_size=32
+	nsim_isa_atomic_option=1
+	nsim_isa_ll64_option=1
+	nsim_isa_unaligned_option=1
+	nsim_isa_code_density_option=2
+	nsim_isa_div_rem_option=2
+	nsim_isa_swap_option=1
+	nsim_isa_bitscan_option=1
+	nsim_isa_mpy_option=9
+	nsim_isa_shift_option=3
+	nsim_isa_fpud_div_option=1
+	nsim_isa_fpu_mac_option=1
+	nsim_isa_enable_timer_0=1
+	nsim_isa_timer_0_int_level=1
+	nsim_isa_enable_timer_1=1
+	nsim_isa_timer_1_int_level=0
+	nsim_isa_rtc_option=1
+	nsim_isa_num_actionpoints=8
+	nsim_isa_stack_checking=1
+	nsim_isa_number_of_interrupts=72
+	nsim_isa_number_of_levels=2
+	nsim_isa_number_of_external_interrupts=70
+	nsim_isa_fast_irq=1
+	nsim_isa_intvbase_preset=0x0
+	dcache=65536,64,2,a
+	nsim_isa_dc_feature_level=2
+	nsim_isa_dc_uncached_region=1
+	nsim_isa_dc_mem_cycles=2
+	icache=65536,64,4,a
+	nsim_isa_ic_feature_level=2
+	dccm_size=0x40000
+	dccm_base=0x80000000
+	nsim_isa_dccm_mem_cycles=2
+	iccm0_size=0x40000
+	iccm0_base=0x70000000
+	nsim_mem-dev=uart0,base=0xf0000000,irq=24

cmake/emu/nsim.cmake

@@ -9,6 +9,8 @@ if(${CONFIG_SOC_NSIM_EM})
  set(NSIM_PROPS nsim_em.props)
 elseif(${CONFIG_SOC_NSIM_SEM})
  set(NSIM_PROPS nsim_sem.props)
+elseif(${CONFIG_SOC_NSIM_HS})
+ set(NSIM_PROPS nsim_hs.props)
 endif()
 
 add_custom_target(run

soc/arc/snps_nsim/Kconfig

@@ -21,6 +21,10 @@ config SOC_NSIM_SEM
 	select CPU_HAS_FPU
 	select ARC_HAS_SECURE
 
+config SOC_NSIM_HS
+	bool "Synopsys ARC HS in nSIM"
+	select CPU_HAS_FPU
+
 endchoice
 
 endif #SOC_NSIM

soc/arc/snps_nsim/Kconfig.defconfig

@@ -16,5 +16,6 @@ config UART_CONSOLE_ON_DEV_NAME
 
 source "soc/arc/snps_nsim/Kconfig.defconfig.em"
 source "soc/arc/snps_nsim/Kconfig.defconfig.sem"
+source "soc/arc/snps_nsim/Kconfig.defconfig.hs"
 
 endif #SOC_NSIM

soc/arc/snps_nsim/Kconfig.defconfig.hs

@@ -0,0 +1,33 @@
+#
+# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_NSIM_HS
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 16 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-15 for Regular Interrupts (IRQs).
+	default 2
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 20
+
+config RGF_NUM_BANKS
+	default 2
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 5000000
+
+config HARVARD
+	default y
+
+config ARC_FIRQ
+	default y
+
+config CACHE_FLUSHING
+	default y
+
+endif #SOC_NSIM_HS