rtc: dw: Add support for optional clock gating
Clock gating is platform specific and not mandatory. Thus making in Kconfig based as well as generic. Change-Id: I01b7831536efd87cc66a95060fcf1faf4a340073 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
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d1d66a6200
commit
61c15ba1e1
6 changed files with 73 additions and 9 deletions
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@ -136,7 +136,6 @@ struct scss_interrupt {
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/* RTC */
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#define RTC_DW_INT_MASK (SCSS_INT_BASE + 0x78)
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#define CCU_RTC_CLK_DIV_OFFSET 0x3
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#define CCU_RTC_PCLK_EN_SW (1 << 11)
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@ -179,6 +179,12 @@ endif
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if RTC
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config RTC_DW
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def_bool y
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config RTC_DW_CLOCK_GATE
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def_bool n
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config RTC_DW_CLOCK_GATE_DRV_NAME
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default CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
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config RTC_DW_CLOCK_GATE_SUBSYS
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default 11
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config RTC_DW_BASE_ADDR
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default 0xB0000400
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config RTC_DW_IRQ
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@ -227,7 +227,6 @@ struct scss_interrupt {
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/* RTC */
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#define RTC_DW_INT_MASK (SCSS_INT_BASE + 0x78)
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#define CCU_RTC_CLK_DIV_OFFSET (3)
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#define CCU_RTC_PCLK_EN_SW (1 << 11)
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/* Clock */
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#define CLOCK_PERIPHERAL_BASE_ADDR (SCSS_REGISTER_BASE + 0x18)
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@ -40,6 +40,24 @@ config RTC_DW_DRV_NAME
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help
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Designware RTC driver instance name
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config RTC_DW_CLOCK_GATE
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bool "Enable clock gating"
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depends on RTC_DW
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select CLOCK_CONTROL
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default n
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help
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Enable clock gating on RTC DesignWare controller
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config RTC_DW_CLOCK_GATE_DRV_NAME
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string "Clock gating driver name"
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depends on RTC_DW_CLOCK_GATE
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default ""
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config RTC_DW_CLOCK_GATE_SUBSYS
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int "Clock controller's subsystem"
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depends on RTC_DW_CLOCK_GATE
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default 0
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config RTC_DW_BASE_ADDR
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hex "Base address"
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depends on RTC_DW
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@ -19,6 +19,7 @@
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#include <stdio.h>
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#include <rtc.h>
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#include <init.h>
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#include <clock_control.h>
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#include "board.h"
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#include "rtc_dw.h"
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@ -36,6 +37,41 @@ static inline void _rtc_dw_int_unmask(void)
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#define _rtc_dw_int_unmask()
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#endif
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#ifdef CONFIG_RTC_DW_CLOCK_GATE
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static inline void _rtc_dw_clock_config(struct device *dev)
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{
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char *drv = CONFIG_RTC_DW_CLOCK_GATE_DRV_NAME;
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struct device *clk;
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clk = device_get_binding(drv);
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if (clk) {
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struct rtc_dw_runtime *context = dev->driver_data;
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context->clock = clk;
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}
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}
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static inline void _rtc_dw_clock_on(struct device *dev)
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{
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struct rtc_dw_dev_config *config = dev->config->config_info;
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struct rtc_dw_runtime *context = dev->driver_data;
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clock_control_on(context->clock, config->clock_data);
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}
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static inline void _rtc_dw_clock_off(struct device *dev)
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{
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struct rtc_dw_dev_config *config = dev->config->config_info;
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struct rtc_dw_runtime *context = dev->driver_data;
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clock_control_off(context->clock, config->clock_data);
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}
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#else
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#define _rtc_dw_clock_config(...)
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#define _rtc_dw_clock_on(...)
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#define _rtc_dw_clock_off(...)
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#endif
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static void rtc_dw_set_div(const enum clk_rtc_div div)
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{
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/* set default division mask */
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@ -53,10 +89,7 @@ static void rtc_dw_set_div(const enum clk_rtc_div div)
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*/
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static void rtc_dw_enable(struct device *dev)
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{
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ARG_UNUSED(dev);
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sys_set_bit(CLOCK_PERIPHERAL_BASE_ADDR, 11);
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sys_set_bit(CLOCK_PERIPHERAL_BASE_ADDR, 1);
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_rtc_dw_clock_on(dev);
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}
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/**
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@ -65,9 +98,7 @@ static void rtc_dw_enable(struct device *dev)
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*/
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static void rtc_dw_disable(struct device *dev)
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{
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ARG_UNUSED(dev);
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sys_clear_bit(CLOCK_PERIPHERAL_BASE_ADDR, 11);
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_rtc_dw_clock_off(dev);
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}
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/**
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@ -169,6 +200,8 @@ int rtc_dw_init(struct device *dev)
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_rtc_dw_int_unmask();
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_rtc_dw_clock_config(dev);
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dev->driver_api = &funcs;
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return DEV_OK;
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@ -178,6 +211,9 @@ struct rtc_dw_runtime rtc_runtime;
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struct rtc_dw_dev_config rtc_dev = {
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.base_address = CONFIG_RTC_DW_BASE_ADDR,
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#ifdef CONFIG_RTC_DW_CLOCK_GATE
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.clock_data = UINT_TO_POINTER(CONFIG_RTC_DW_CLOCK_GATE_SUBSYS),
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#endif
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};
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DECLARE_DEVICE_INIT_CONFIG(rtc, CONFIG_RTC_DW_DRV_NAME,
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@ -44,10 +44,16 @@
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struct rtc_dw_runtime {
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void (*rtc_dw_cb_fn)(struct device *dev);
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#ifdef CONFIG_RTC_DW_CLOCK_GATE
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struct device *clock;
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#endif
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};
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struct rtc_dw_dev_config {
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uint32_t base_address;
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#ifdef CONFIG_RTC_DW_CLOCK_GATE
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void *clock_data;
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#endif
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};
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int rtc_dw_init(struct device *dev);
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