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drivers/clock_control: stm32h7: Change clock bus bindings values

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Set bus binding values using registers offset values.
As a consequence update driver to take this into account
in clock_on and clock_off functions.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2022-01-14 11:25:39 +01:00 • committed by Carles Cufí
commit 61a9016f88
3 changed files with 44 additions and 87 deletions
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99
drivers/clock_control/clock_stm32_ll_h7.c
View file

@ -314,97 +314,52 @@ static inline int stm32_clock_control_on(const struct device *dev,
clock_control_subsys_t sub_system) clock_control_subsys_t sub_system)
{ {
struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
int rc = 0; volatile uint32_t *reg;
uint32_t reg_val;
ARG_UNUSED(dev); ARG_UNUSED(dev);
/* Both cores can access banks by following LL API */ if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
/* Using "_Cn_" LL API would restrict access to one or the other */ /* Attemp to toggle a wrong periph clock bit */
z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY); return -ENOTSUP;
switch (pclken->bus) {
case STM32_CLOCK_BUS_AHB1:
LL_AHB1_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB2:
LL_AHB2_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB3:
LL_AHB3_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB4:
LL_AHB4_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB1:
LL_APB1_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB1_2:
LL_APB1_GRP2_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB2:
LL_APB2_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB3:
LL_APB3_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB4:
LL_APB4_GRP1_EnableClock(pclken->enr);
break;
default:
rc = -ENOTSUP;
break;
} }
z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
reg = (uint32_t *)(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);
reg_val = *reg;
reg_val |= pclken->enr;
*reg = reg_val;
z_stm32_hsem_unlock(CFG_HW_RCC_SEMID); z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
return rc; return 0;
} }
static inline int stm32_clock_control_off(const struct device *dev, static inline int stm32_clock_control_off(const struct device *dev,
clock_control_subsys_t sub_system) clock_control_subsys_t sub_system)
{ {
struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
int rc = 0; volatile uint32_t *reg;
uint32_t reg_val;
ARG_UNUSED(dev); ARG_UNUSED(dev);
/* Both cores can access banks by following LL API */ if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
/* Using "_Cn_" LL API would restrict access to one or the other */ /* Attemp to toggle a wrong periph clock bit */
z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY); return -ENOTSUP;
switch (pclken->bus) {
case STM32_CLOCK_BUS_AHB1:
LL_AHB1_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB2:
LL_AHB2_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB3:
LL_AHB3_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB4:
LL_AHB4_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB1:
LL_APB1_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB1_2:
LL_APB1_GRP2_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB2:
LL_APB2_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB3:
LL_APB3_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB4:
LL_APB4_GRP1_DisableClock(pclken->enr);
break;
default:
rc = -ENOTSUP;
break;
} }
z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
reg = (uint32_t *)(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);
reg_val = *reg;
reg_val &= ~pclken->enr;
*reg = reg_val;
z_stm32_hsem_unlock(CFG_HW_RCC_SEMID); z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
return rc; return 0;
} }
static int stm32_clock_control_get_subsys_rate(const struct device *clock, static int stm32_clock_control_get_subsys_rate(const struct device *clock,

27
include/dt-bindings/clock/stm32h7_clock.h
View file

@ -7,20 +7,17 @@
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_
/* clock bus references */ /* clock bus references */
#define STM32_CLOCK_BUS_AHB1 0 #define STM32_CLOCK_BUS_AHB3 0x0D4
#define STM32_CLOCK_BUS_AHB2 1 #define STM32_CLOCK_BUS_AHB1 0x0D8
#define STM32_CLOCK_BUS_APB1 2 #define STM32_CLOCK_BUS_AHB2 0x0DC
#define STM32_CLOCK_BUS_APB2 3 #define STM32_CLOCK_BUS_AHB4 0x0E0
#define STM32_CLOCK_BUS_APB1_2 4 #define STM32_CLOCK_BUS_APB3 0x0E4
#define STM32_CLOCK_BUS_IOP 5 #define STM32_CLOCK_BUS_APB1 0x0E8
#define STM32_CLOCK_BUS_AHB3 6 #define STM32_CLOCK_BUS_APB1_2 0x0EC
#define STM32_CLOCK_BUS_AHB4 7 #define STM32_CLOCK_BUS_APB2 0x0F0
#define STM32_CLOCK_BUS_AHB5 8 #define STM32_CLOCK_BUS_APB4 0x0F4
#define STM32_CLOCK_BUS_AHB6 9
#define STM32_CLOCK_BUS_APB3 10 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB3
#define STM32_CLOCK_BUS_APB4 11 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB4
#define STM32_CLOCK_BUS_APB5 12
#define STM32_CLOCK_BUS_AXI 13
#define STM32_CLOCK_BUS_MLAHB 14
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_ */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_ */

5
include/zephyr/drivers/clock_control/stm32_clock_control.h
View file

@ -10,7 +10,12 @@
#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ #define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_
#include <drivers/clock_control.h> #include <drivers/clock_control.h>
#if !defined(CONFIG_SOC_SERIES_STM32H7X)
#include <dt-bindings/clock/stm32_clock.h> #include <dt-bindings/clock/stm32_clock.h>
#else
#include <dt-bindings/clock/stm32h7_clock.h>
#endif
/** Common clock control device node for all STM32 chips */ /** Common clock control device node for all STM32 chips */
#define STM32_CLOCK_CONTROL_NODE DT_NODELABEL(rcc) #define STM32_CLOCK_CONTROL_NODE DT_NODELABEL(rcc)