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riscv: Rename RISCV_MTVEC_VECTORED_MODE to RISCV_VECTORED_MODE

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Before adding support for the CLIC vectored mode, rename
CONFIG_RISCV_MTVEC_VECTORED_MODE to CONFIG_RISCV_VECTORED_MODE to be
more generic and eventually include also the CLIC vectored mode.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
Carlo Caione 2023-06-06 15:19:25 +02:00 • committed by Anas Nashif
commit 6160383ec7
4 changed files with 7 additions and 7 deletions
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2
arch/riscv/Kconfig
View file

@ -301,7 +301,7 @@ config ARCH_IRQ_VECTOR_TABLE_ALIGN
default 256 default 256
config GEN_IRQ_VECTOR_TABLE config GEN_IRQ_VECTOR_TABLE
select RISCV_MTVEC_VECTORED_MODE if SOC_FAMILY_RISCV_PRIVILEGED select RISCV_VECTORED_MODE if SOC_FAMILY_RISCV_PRIVILEGED
config ARCH_HAS_SINGLE_THREAD_SUPPORT config ARCH_HAS_SINGLE_THREAD_SUPPORT
default y if !SMP default y if !SMP

6
soc/riscv/riscv-privileged/Kconfig
View file

@ -28,10 +28,10 @@ config RISCV_HAS_CLIC
help help
Does the SOC provide support for a Core-Local Interrupt Controller (CLIC). Does the SOC provide support for a Core-Local Interrupt Controller (CLIC).
config RISCV_MTVEC_VECTORED_MODE config RISCV_VECTORED_MODE
bool "Should the SOC use mtvec in vectored mode" bool "Should the SOC use vectored mode"
depends on SOC_FAMILY_RISCV_PRIVILEGED depends on SOC_FAMILY_RISCV_PRIVILEGED
help help
Should the SOC use mtvec in vectored mode Should the SOC use vectored mode.
source "soc/riscv/riscv-privileged/*/Kconfig.soc" source "soc/riscv/riscv-privileged/*/Kconfig.soc"

4
soc/riscv/riscv-privileged/common/vector.S
View file

@ -25,7 +25,7 @@ SECTION_FUNC(vectors, __start)
.option norvc; .option norvc;
#if defined(CONFIG_RISCV_MTVEC_VECTORED_MODE) #if defined(CONFIG_RISCV_VECTORED_MODE)
/* /*
* Set mtvec (Machine Trap-Vector Base-Address Register) * Set mtvec (Machine Trap-Vector Base-Address Register)
* to _irq_vector_table (interrupt vector table). Add 1 to base * to _irq_vector_table (interrupt vector table). Add 1 to base
@ -39,7 +39,7 @@ SECTION_FUNC(vectors, __start)
la t0, _irq_vector_table /* Load address of interrupt vector table */ la t0, _irq_vector_table /* Load address of interrupt vector table */
addi t0, t0, 1 /* Enable vectored mode by setting LSB */ addi t0, t0, 1 /* Enable vectored mode by setting LSB */
/* MTVEC_DIRECT_MODE */ /* DIRECT_MODE */
#else #else
/* /*
* Set mtvec (Machine Trap-Vector Base-Address Register) * Set mtvec (Machine Trap-Vector Base-Address Register)

2
soc/riscv/riscv-privileged/opentitan/Kconfig.series
View file

@ -6,7 +6,7 @@ config SOC_SERIES_RISCV_OPENTITAN
select RISCV select RISCV
select SOC_FAMILY_RISCV_PRIVILEGED select SOC_FAMILY_RISCV_PRIVILEGED
# OpenTitan Ibex core mtvec mode is read-only / forced to vectored mode. # OpenTitan Ibex core mtvec mode is read-only / forced to vectored mode.
select RISCV_MTVEC_VECTORED_MODE select RISCV_VECTORED_MODE
select GEN_IRQ_VECTOR_TABLE select GEN_IRQ_VECTOR_TABLE
help help
Enable support for OpenTitan Enable support for OpenTitan