diff --git a/arch/xtensa/core/crt1.S b/arch/xtensa/core/crt1.S
index b012f29197d..23ce498df9e 100644
--- a/arch/xtensa/core/crt1.S
+++ b/arch/xtensa/core/crt1.S
@@ -204,7 +204,12 @@ _start:
 	rsr     a3, PRID
 	extui   a3, a3, 0, 8	/* extract core ID */
 	beqz    a3, 2f
-	CALL    z_mp_entry
+
+	/* Load our stack pointer set up for us by the SOC layer */
+	movi    a1, z_mp_stack_top
+	l32i    a1, a1, 0
+
+	call4 z_mp_entry
 
 2:
 #endif
diff --git a/soc/xtensa/intel_adsp/common/soc_mp.c b/soc/xtensa/intel_adsp/common/soc_mp.c
index 4b1d1e8fe1b..6984a4fa775 100644
--- a/soc/xtensa/intel_adsp/common/soc_mp.c
+++ b/soc/xtensa/intel_adsp/common/soc_mp.c
@@ -61,13 +61,14 @@ struct cpustart_rec {
 	uint32_t		cpu;
 
 	arch_cpustart_t	fn;
-	char		*stack_top;
 	void		*arg;
 	uint32_t		vecbase;
 
 	uint32_t		alive;
 };
 
+char *z_mp_stack_top;
+
 #ifdef CONFIG_KERNEL_COHERENCE
 /* Coherence guarantees that normal .data will be coherent and that it
  * won't overlap any cached memory.
@@ -158,11 +159,12 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
 
 	start_rec.cpu = cpu_num;
 	start_rec.fn = fn;
-	start_rec.stack_top = Z_THREAD_STACK_BUFFER(stack) + sz;
 	start_rec.arg = arg;
 	start_rec.vecbase = vecbase;
 	start_rec.alive = 0;
 
+	z_mp_stack_top = Z_THREAD_STACK_BUFFER(stack) + sz;
+
 #ifdef CONFIG_IPM_CAVS_IDC
 	idc = device_get_binding(DT_LABEL(DT_INST(0, intel_cavs_idc)));
 #endif