From 60a41f68782d0f6c9c61b6c59d128adebb3b5e29 Mon Sep 17 00:00:00 2001
From: Jay Vasanth <jay.vasanth@microchip.com>
Date: Fri, 8 Apr 2022 18:03:26 -0400
Subject: [PATCH] drivers: ps2: Microchip XEC PS2 add MEC172x support

Update the Microchip XEC PS2 driver to support MEC172x.
NOTE: MEC15xx has two PS2 controllers and
MEC172x has one.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
---
 drivers/ps2/Kconfig.xec                       |  3 ++-
 drivers/ps2/ps2_mchp_xec.c                    | 27 +++++++++++++++++++
 dts/arm/microchip/mec172xnsz.dtsi             |  2 +-
 .../mec172x/Kconfig.defconfig.series          |  4 +++
 4 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/drivers/ps2/Kconfig.xec b/drivers/ps2/Kconfig.xec
index 0ace21a7467..89a23b97da4 100644
--- a/drivers/ps2/Kconfig.xec
+++ b/drivers/ps2/Kconfig.xec
@@ -8,4 +8,5 @@ config PS2_XEC
 	depends on SOC_FAMILY_MEC && ESPI_PERIPHERAL_8042_KBC
 	help
 	  Enable the Microchip XEC PS2 IO driver. The driver also
-	  depends on the KBC 8042 keyboard controller.
+	  depends on the KBC 8042 keyboard controller. Note, MEC15xx
+	  series has two controllers and MEC172x series has one.
diff --git a/drivers/ps2/ps2_mchp_xec.c b/drivers/ps2/ps2_mchp_xec.c
index 659c981b01d..982033fe69f 100644
--- a/drivers/ps2/ps2_mchp_xec.c
+++ b/drivers/ps2/ps2_mchp_xec.c
@@ -10,6 +10,10 @@
 #include <arch/arm/aarch32/cortex_m/cmsis.h>
 #include <errno.h>
 #include <device.h>
+#ifdef CONFIG_SOC_SERIES_MEC172X
+#include <drivers/clock_control/mchp_xec_clock_control.h>
+#include <drivers/interrupt_controller/intc_mchp_xec_ecia.h>
+#endif
 #include <drivers/ps2.h>
 #include <soc.h>
 #include <logging/log.h>
@@ -35,6 +39,28 @@ struct ps2_xec_data {
 	struct k_sem tx_lock;
 };
 
+#ifdef CONFIG_SOC_SERIES_MEC172X
+static inline void ps2_xec_slp_en_clr(const struct device *dev)
+{
+	const struct ps2_xec_config * const cfg = dev->config;
+
+	z_mchp_xec_pcr_periph_sleep(cfg->pcr_idx, cfg->pcr_pos, 0);
+}
+
+static inline void ps2_xec_girq_clr(const struct device *dev)
+{
+	const struct ps2_xec_config * const cfg = dev->config;
+
+	mchp_soc_ecia_girq_src_clr(cfg->girq_id, cfg->girq_bit);
+}
+
+static inline void ps2_xec_girq_en(const struct device *dev)
+{
+	const struct ps2_xec_config * const cfg = dev->config;
+
+	mchp_xec_ecia_girq_src_en(cfg->girq_id, cfg->girq_bit);
+}
+#else
 static inline void ps2_xec_slp_en_clr(const struct device *dev)
 {
 	const struct ps2_xec_config * const cfg = dev->config;
@@ -59,6 +85,7 @@ static inline void ps2_xec_girq_en(const struct device *dev)
 
 	MCHP_GIRQ_ENSET(cfg->girq_id) = BIT(cfg->girq_bit);
 }
+#endif /* CONFIG_SOC_SERIES_MEC172X */
 
 static int ps2_xec_configure(const struct device *dev,
 			     ps2_callback_t callback_isr)
diff --git a/dts/arm/microchip/mec172xnsz.dtsi b/dts/arm/microchip/mec172xnsz.dtsi
index 3d59b5d578f..597bcff4ecf 100644
--- a/dts/arm/microchip/mec172xnsz.dtsi
+++ b/dts/arm/microchip/mec172xnsz.dtsi
@@ -575,8 +575,8 @@
 			#size-cells = <0>;
 			status = "disabled";
 		};
-/* uarts were here */
 		ps2_0: ps2@40009000 {
+			compatible = "microchip,xec-ps2";
 			reg = <0x40009000 0x40>;
 			interrupts = <100 1>;
 			girqs = <18 10>;
diff --git a/soc/arm/microchip_mec/mec172x/Kconfig.defconfig.series b/soc/arm/microchip_mec/mec172x/Kconfig.defconfig.series
index bc1f6452e34..451c7146ee3 100644
--- a/soc/arm/microchip_mec/mec172x/Kconfig.defconfig.series
+++ b/soc/arm/microchip_mec/mec172x/Kconfig.defconfig.series
@@ -39,4 +39,8 @@ config CLOCK_CONTROL_MCHP_XEC
 config MCHP_ECIA_XEC
 	default y
 
+config PS2_XEC
+	default y
+	depends on PS2
+
 endif # SOC_SERIES_MEC172X