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xtensa: cache: XCC needs to declare variable outside for loop

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XCC doesn't like that a for loop which declares the loop
variable inline. So extract the declaration of the loop
variable outside the for loop.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2021-07-01 11:47:38 -07:00 • committed by Anas Nashif
commit 605cad1190
1 changed files with 6 additions and 3 deletions
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9
include/arch/xtensa/cache.h
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@ -26,8 +26,9 @@ static inline void z_xtensa_cache_flush(void *addr, size_t bytes)
size_t step = XCHAL_DCACHE_LINESIZE; size_t step = XCHAL_DCACHE_LINESIZE;
size_t first = ROUND_DOWN(addr, step); size_t first = ROUND_DOWN(addr, step);
size_t last = ROUND_UP(((long)addr) + bytes, step); size_t last = ROUND_UP(((long)addr) + bytes, step);
size_t line;
for (size_t line = first; bytes && line < last; line += step) { for (line = first; bytes && line < last; line += step) {
__asm__ volatile("dhwb %0, 0" :: "r"(line)); __asm__ volatile("dhwb %0, 0" :: "r"(line));
} }
#endif #endif
@ -39,8 +40,9 @@ static inline void z_xtensa_cache_flush_inv(void *addr, size_t bytes)
size_t step = XCHAL_DCACHE_LINESIZE; size_t step = XCHAL_DCACHE_LINESIZE;
size_t first = ROUND_DOWN(addr, step); size_t first = ROUND_DOWN(addr, step);
size_t last = ROUND_UP(((long)addr) + bytes, step); size_t last = ROUND_UP(((long)addr) + bytes, step);
size_t line;
for (size_t line = first; bytes && line < last; line += step) { for (line = first; bytes && line < last; line += step) {
__asm__ volatile("dhwbi %0, 0" :: "r"(line)); __asm__ volatile("dhwbi %0, 0" :: "r"(line));
} }
#endif #endif
@ -52,8 +54,9 @@ static inline void z_xtensa_cache_inv(void *addr, size_t bytes)
size_t step = XCHAL_DCACHE_LINESIZE; size_t step = XCHAL_DCACHE_LINESIZE;
size_t first = ROUND_DOWN(addr, step); size_t first = ROUND_DOWN(addr, step);
size_t last = ROUND_UP(((long)addr) + bytes, step); size_t last = ROUND_UP(((long)addr) + bytes, step);
size_t line;
for (size_t line = first; bytes && line < last; line += step) { for (line = first; bytes && line < last; line += step) {
__asm__ volatile("dhi %0, 0" :: "r"(line)); __asm__ volatile("dhi %0, 0" :: "r"(line));
} }
#endif #endif