arch: riscv: pmp: fix IRQ handling of PMP stack guard
This commit add 2 minor fixes of IRQ handling: 1. Save caller registers before calling z_riscv_configure_stack_guard() in RISC-V assembly. 2. reschedule and no_reschdule code paths use different interrupt return path after supporting of CONFIG_PMP_STACK_GUARD. back-to-back interrupt checking is in the reschedule code path so that it should jump to interrupt return path of reschedule. Signed-off-by: Jim Shu <cwshu09@gmail.com>
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1 changed files with 19 additions and 2 deletions
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@ -831,7 +831,7 @@ reschedule:
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la t0, _kernel
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la t0, _kernel
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RV_OP_LOADREG t2, _kernel_offset_to_current(t0)
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RV_OP_LOADREG t2, _kernel_offset_to_current(t0)
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RV_OP_LOADREG t3, _kernel_offset_to_ready_q_cache(t0)
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RV_OP_LOADREG t3, _kernel_offset_to_ready_q_cache(t0)
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beq t2, t3, no_reschedule
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beq t2, t3, no_reschedule_resched
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#if CONFIG_INSTRUMENT_THREAD_SWITCHING
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#if CONFIG_INSTRUMENT_THREAD_SWITCHING
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call z_thread_mark_switched_out
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call z_thread_mark_switched_out
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@ -925,8 +925,16 @@ skip_load_fp_callee_saved:
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#ifdef CONFIG_PMP_STACK_GUARD
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#ifdef CONFIG_PMP_STACK_GUARD
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mv a0, t1 /* kernel current */
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mv a0, t1 /* kernel current */
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/* Save t0/t1 caller registers for function call */
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addi sp, sp, -16
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RV_OP_STOREREG t0, 0(sp)
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RV_OP_STOREREG t1, 8(sp)
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jal ra, z_riscv_configure_stack_guard
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jal ra, z_riscv_configure_stack_guard
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#endif // CONFIG_PMP_STACK_GUARD
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RV_OP_LOADREG t0, 0(sp)
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RV_OP_LOADREG t1, 8(sp)
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addi sp, sp, 16
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#endif /* CONFIG_PMP_STACK_GUARD */
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#ifdef CONFIG_USERSPACE
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#ifdef CONFIG_USERSPACE
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/* t0 still reference to _kernel */
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/* t0 still reference to _kernel */
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@ -957,6 +965,15 @@ kernel_swap:
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call z_thread_mark_switched_in
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call z_thread_mark_switched_in
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#endif
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#endif
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/*
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* no_reschedule_resched is an another interrupt return path.
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*
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* When CONFIG_PMP_STACK_GUARD=y, reschedule & no_reschedule
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* code paths use different sp and only no_reschedule code path
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* needs to switch sp before interrupt return. Thus, we use
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* another interrupt return path for reschedule path.
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*/
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no_reschedule_resched:
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#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
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#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
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/* Restore context at SOC level */
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/* Restore context at SOC level */
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addi a0, sp, __z_arch_esf_t_soc_context_OFFSET
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addi a0, sp, __z_arch_esf_t_soc_context_OFFSET
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