ite: drivers/adc: it8xxx2: fix adc driver flow
This commit fixes the ADC driver flow. And add internal reference voltage to ADC driver API. And correct the data buffer that only need to store raw data. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit is contained in:
Tim Lin
Anas Nashif
parent
bb40d93f27
commit
5f5fb7d792
2 changed files with 125 additions and 159 deletions
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@ -11,6 +11,7 @@
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LOG_MODULE_REGISTER(adc_ite_it8xxx2);
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#include <drivers/adc.h>
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#include <drivers/pinmux.h>
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#include <soc.h>
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#include <errno.h>
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#include <assert.h>
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@ -20,27 +21,10 @@ LOG_MODULE_REGISTER(adc_ite_it8xxx2);
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#define DEV_DATA(dev) ((struct adc_it8xxx2_data * const)(dev)->data)
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/* Data structure to define ADC channel control registers. */
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struct adc_ctrl_t {
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/* The voltage channel control register. */
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volatile uint8_t *adc_ctrl;
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/* The voltage channel data buffer MSB. */
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volatile uint8_t *adc_datm;
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/* The voltage channel data buffer LSB. */
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volatile uint8_t *adc_datl;
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};
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/* Data structure of ADC channel control registers. */
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static const struct adc_ctrl_t adc_ctrl_regs[] = {
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{&IT83XX_ADC_VCH0CTL, &IT83XX_ADC_VCH0DATM, &IT83XX_ADC_VCH0DATL},
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{&IT83XX_ADC_VCH1CTL, &IT83XX_ADC_VCH1DATM, &IT83XX_ADC_VCH1DATL},
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{&IT83XX_ADC_VCH2CTL, &IT83XX_ADC_VCH2DATM, &IT83XX_ADC_VCH2DATL},
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{&IT83XX_ADC_VCH3CTL, &IT83XX_ADC_VCH3DATM, &IT83XX_ADC_VCH3DATL},
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{&IT83XX_ADC_VCH4CTL, &IT83XX_ADC_VCH4DATM, &IT83XX_ADC_VCH4DATL},
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{&IT83XX_ADC_VCH5CTL, &IT83XX_ADC_VCH5DATM, &IT83XX_ADC_VCH5DATL},
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{&IT83XX_ADC_VCH6CTL, &IT83XX_ADC_VCH6DATM, &IT83XX_ADC_VCH6DATL},
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{&IT83XX_ADC_VCH7CTL, &IT83XX_ADC_VCH7DATM, &IT83XX_ADC_VCH7DATL},
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};
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/* ADC internal reference voltage (Unit:mV) */
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#define IT8XXX2_ADC_VREF_VOL 3000
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/* ADC channels disabled */
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#define IT8XXX2_ADC_CHANNEL_DISABLED 0x1F
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/* List of ADC channels. */
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enum chip_adc_channel {
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@ -57,6 +41,8 @@ enum chip_adc_channel {
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struct adc_it8xxx2_data {
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struct adc_context ctx;
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/* Channel ID */
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uint32_t ch;
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/* Save ADC result to the buffer. */
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uint16_t *buffer;
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/*
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@ -66,10 +52,14 @@ struct adc_it8xxx2_data {
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uint16_t *repeat_buffer;
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};
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#define ADC_IT8XXX2_REG_BASE \
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((struct adc_it8xxx2_regs *)(DT_INST_REG_ADDR(0)))
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static int adc_it8xxx2_channel_setup(const struct device *dev,
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const struct adc_channel_cfg *channel_cfg)
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const struct adc_channel_cfg *channel_cfg)
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{
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ARG_UNUSED(dev);
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const struct device *porti = DEVICE_DT_GET(DT_NODELABEL(pinmuxi));
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if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
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LOG_ERR("Selected ADC acquisition time is not valid");
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@ -91,36 +81,41 @@ static int adc_it8xxx2_channel_setup(const struct device *dev,
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return -EINVAL;
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}
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if (channel_cfg->channel_id < CHIP_ADC_CH4) {
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/* For channel 0 ~ 3 control register. */
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*adc_ctrl_regs[channel_cfg->channel_id].adc_ctrl =
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(IT83XX_ADC_DATVAL | IT83XX_ADC_INTDVEN) +
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channel_cfg->channel_id;
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} else {
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/* For channel 4 ~ 7 control register. */
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*adc_ctrl_regs[channel_cfg->channel_id].adc_ctrl =
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IT83XX_ADC_DATVAL | IT83XX_ADC_INTDVEN | IT83XX_ADC_VCHEN;
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}
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/* The channel is set to ADC alternate function */
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pinmux_pin_set(porti, channel_cfg->channel_id, IT8XXX2_PINMUX_FUNC_1);
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LOG_DBG("Channel setup succeeded!");
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return 0;
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}
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static uint8_t count_channels(uint8_t ch)
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static void adc_enable_measurement(uint32_t ch)
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{
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uint8_t count = 0;
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uint8_t bit;
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struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
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bit = find_lsb_set(ch);
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while (bit != 0) {
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uint8_t idx = bit - 1;
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/* Select and enable a voltage channel input for measurement */
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adc_regs->VCH0CTL = (IT8XXX2_ADC_DATVAL | IT8XXX2_ADC_INTDVEN) + ch;
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ch &= ~BIT(idx);
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bit = find_lsb_set(ch);
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count++;
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}
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/* Enable adc interrupt */
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irq_enable(DT_INST_IRQN(0));
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return count;
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/* ADC module enable */
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adc_regs->ADCCFG |= IT8XXX2_ADC_ADCEN;
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}
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static void adc_disable_measurement(void)
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{
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struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
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/*
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* Disable measurement.
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* bit(4:0) = 0x1f : channel disable
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*/
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adc_regs->VCH0CTL = IT8XXX2_ADC_DATVAL | IT8XXX2_ADC_CHANNEL_DISABLED;
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/* ADC module disable */
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adc_regs->ADCCFG &= ~IT8XXX2_ADC_ADCEN;
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/* disable adc interrupt */
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irq_disable(DT_INST_IRQN(0));
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}
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static int check_buffer_size(const struct adc_sequence *sequence,
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@ -143,14 +138,12 @@ static int check_buffer_size(const struct adc_sequence *sequence,
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}
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static int adc_it8xxx2_start_read(const struct device *dev,
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const struct adc_sequence *sequence)
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const struct adc_sequence *sequence)
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{
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struct adc_it8xxx2_data *data = DEV_DATA(dev);
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uint8_t channels = sequence->channels;
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uint8_t channel_count;
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int err;
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uint32_t channel_mask = sequence->channels;
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if (!channels || channels & ~BIT_MASK(CHIP_ADC_COUNT)) {
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if (!channel_mask || channel_mask & ~BIT_MASK(CHIP_ADC_COUNT)) {
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LOG_ERR("Invalid selection of channels");
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return -EINVAL;
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}
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@ -161,13 +154,6 @@ static int adc_it8xxx2_start_read(const struct device *dev,
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}
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LOG_DBG("Configure resolution=%d", sequence->resolution);
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channel_count = count_channels(channels);
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err = check_buffer_size(sequence, channel_count);
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if (err) {
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return err;
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}
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data->buffer = sequence->buffer;
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adc_context_start_read(&data->ctx, sequence);
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return adc_context_wait_for_completion(&data->ctx);
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@ -180,22 +166,34 @@ static void adc_context_start_sampling(struct adc_context *ctx)
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data->repeat_buffer = data->buffer;
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/* enable adc interrupt */
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irq_enable(DT_INST_IRQN(0));
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/* ADC module enable */
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IT83XX_ADC_ADCCFG |= IT83XX_ADC_ADCEN;
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adc_enable_measurement(data->ch);
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}
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static int adc_it8xxx2_read(const struct device *dev,
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const struct adc_sequence *sequence)
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const struct adc_sequence *sequence)
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{
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struct adc_it8xxx2_data *data = DEV_DATA(dev);
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int err;
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uint32_t channel_mask = sequence->channels;
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uint8_t channel_count = 0;
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int err = 0;
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adc_context_lock(&data->ctx, false, NULL);
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err = adc_it8xxx2_start_read(dev, sequence);
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adc_context_release(&data->ctx, err);
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data->buffer = sequence->buffer;
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while (channel_mask) {
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adc_context_lock(&data->ctx, false, NULL);
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data->ch = find_lsb_set(channel_mask) - 1;
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err = adc_it8xxx2_start_read(dev, sequence);
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if (err) {
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return err;
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}
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channel_mask &= ~BIT(data->ch);
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channel_count++;
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adc_context_release(&data->ctx, err);
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}
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err = check_buffer_size(sequence, channel_count);
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return err;
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}
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@ -211,49 +209,26 @@ static void adc_context_update_buffer_pointer(struct adc_context *ctx,
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}
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}
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static int adc_data_valid(enum chip_adc_channel adc_ch)
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{
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return IT83XX_ADC_ADCDVSTS & BIT(adc_ch);
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}
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/* Get result for each ADC selected channel. */
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static void adc_it8xxx2_get_sample(const struct device *dev)
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{
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struct adc_it8xxx2_data *data = DEV_DATA(dev);
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uint8_t channels = data->ctx.sequence.channels;
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uint8_t bit;
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struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
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bool valid = false;
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bit = find_lsb_set(channels);
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while (bit != 0) {
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uint8_t idx = bit - 1;
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if (adc_regs->VCH0CTL & IT8XXX2_ADC_DATVAL) {
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/* Read adc raw data of msb and lsb */
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*data->buffer++ = adc_regs->VCH0DATM << 8 | adc_regs->VCH0DATL;
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if (adc_data_valid(idx)) {
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/* Read adc raw data of msb and lsb */
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uint16_t val = (*adc_ctrl_regs[idx].adc_datm << 8) |
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*adc_ctrl_regs[idx].adc_datl;
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/* Raw data multiply resolution. */
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*data->buffer++ = val * data->ctx.sequence.resolution;
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/* W/C data valid flag */
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IT83XX_ADC_ADCDVSTS = BIT(idx);
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valid = 1;
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}
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if (!valid) {
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LOG_WRN("ADC failed to read (regs=%x, ch=%d)",
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IT83XX_ADC_ADCDVSTS, idx);
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}
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channels &= ~BIT(idx);
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bit = find_lsb_set(channels);
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valid = 1;
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}
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/* ADC module disable */
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IT83XX_ADC_ADCCFG &= ~IT83XX_ADC_ADCEN;
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/* disable adc interrupt */
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irq_disable(DT_INST_IRQN(0));
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if (!valid) {
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LOG_WRN("ADC failed to read (regs=%x, ch=%d)",
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adc_regs->ADCDVSTS, data->ch);
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}
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adc_disable_measurement();
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}
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static void adc_it8xxx2_isr(const void *arg)
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@ -271,6 +246,7 @@ static void adc_it8xxx2_isr(const void *arg)
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static const struct adc_driver_api api_it8xxx2_driver_api = {
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.channel_setup = adc_it8xxx2_channel_setup,
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.read = adc_it8xxx2_read,
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.ref_internal = IT8XXX2_ADC_VREF_VOL,
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};
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/*
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@ -283,19 +259,20 @@ static const struct adc_driver_api api_it8xxx2_driver_api = {
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*/
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static void adc_accuracy_initialization(void)
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{
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struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
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/* Start adc accuracy initialization */
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IT83XX_ADC_ADCSTS |= IT83XX_ADC_AINITB;
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adc_regs->ADCSTS |= IT8XXX2_ADC_AINITB;
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/* Enable automatic HW calibration. */
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IT83XX_ADC_KDCTL |= IT83XX_ADC_AHCE;
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/* short delay for adc accuracy initialization */
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IT83XX_GCTRL_WNCKR = 0;
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adc_regs->KDCTL |= IT8XXX2_ADC_AHCE;
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/* Stop adc accuracy initialization */
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IT83XX_ADC_ADCSTS &= ~IT83XX_ADC_AINITB;
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adc_regs->ADCSTS &= ~IT8XXX2_ADC_AINITB;
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}
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static int adc_it8xxx2_init(const struct device *dev)
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{
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struct adc_it8xxx2_data *data = DEV_DATA(dev);
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struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
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/* ADC analog accuracy initialization */
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adc_accuracy_initialization();
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@ -307,13 +284,18 @@ static int adc_it8xxx2_init(const struct device *dev)
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* NOTE: A sample time delay (60us) also need to be included in
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* conversion time, so the final result is ~= 121.6us.
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*/
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IT83XX_ADC_ADCSTS &= ~IT83XX_ADC_ADCCTS1;
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IT83XX_ADC_ADCCFG &= ~IT83XX_ADC_ADCCTS0;
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adc_regs->ADCSTS &= ~IT8XXX2_ADC_ADCCTS1;
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adc_regs->ADCCFG &= ~IT8XXX2_ADC_ADCCTS0;
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/*
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* bit[5-0]@ADCCTL : SCLKDIV
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* SCLKDIV has to be equal to or greater than 1h;
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*/
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IT83XX_ADC_ADCCTL = 1;
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adc_regs->ADCCTL = 1;
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/*
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* Enable this bit, and data of VCHxDATL/VCHxDATM will be
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* kept until data valid is cleared.
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*/
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adc_regs->ADCGCR |= IT8XXX2_ADC_DBKEN;
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IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
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adc_it8xxx2_isr, DEVICE_DT_INST_GET(0), 0);
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@ -329,8 +311,8 @@ static struct adc_it8xxx2_data adc_it8xxx2_data_0 = {
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ADC_CONTEXT_INIT_SYNC(adc_it8xxx2_data_0, ctx),
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};
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DEVICE_DT_INST_DEFINE(0, adc_it8xxx2_init,
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NULL,
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&adc_it8xxx2_data_0,
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NULL, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&api_it8xxx2_driver_api);
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NULL,
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&adc_it8xxx2_data_0,
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NULL, PRE_KERNEL_1,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&api_it8xxx2_driver_api);
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