diff --git a/dts/arm/renesas/ra/ra6/r7fa6m2af3cfb.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m2af3cfb.dtsi new file mode 100644 index 00000000000..4a3320b2bbb --- /dev/null +++ b/dts/arm/renesas/ra/ra6/r7fa6m2af3cfb.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + flash-controller@407e0000 { + compatible = "renesas,ra6-flash-controller"; + reg = <0x407e0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <4 1>, <5 1>; + interrupt-names = "frdyi", "fiferr"; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0x0 DT_SIZE_M(1)>; + write-block-size = <128>; + erase-block-size = <8192>; + }; + }; + }; +}; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi new file mode 100644 index 00000000000..82a6333c293 --- /dev/null +++ b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + sram0: memory@1ffe0000 { + compatible = "mmio-sram"; + reg = <0x1ffe0000 DT_SIZE_K(384)>; + }; + + sci5: sci5@400700a0 { + compatible = "renesas,ra-sci"; + interrupts = <20 1>, <21 1>, <22 1>, <23 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x400700a0 0x20>; + clocks = <&pclka MSTPB 26>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <5>; + status = "disabled"; + }; + }; + + sci6: sci6@400700c0 { + compatible = "renesas,ra-sci"; + interrupts = <24 1>, <25 1>, <26 1>, <27 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x400700c0 0x20>; + clocks = <&pclka MSTPB 25>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <6>; + status = "disabled"; + }; + }; + + sci7: sci7@400700e0 { + compatible = "renesas,ra-sci"; + interrupts = <28 1>, <29 1>, <30 1>, <31 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x400700e0 0x20>; + clocks = <&pclka MSTPB 24>; + status = "disabled"; + uart { + compatible = "renesas,ra-sci-uart"; + channel = <7>; + status = "disabled"; + }; + }; + }; + + clocks: clocks { + xtal: clock-xtal { + compatible = "renesas,ra-cgc-external-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "disabled"; + }; + + hoco: clock-hoco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + moco: clock-moco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + loco: clock-loco { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + subclk: clock-subclk { + compatible = "renesas,ra-cgc-subclk"; + clock-frequency = <32768>; + #clock-cells = <0>; + status = "disabled"; + }; + + pll: pll { + compatible = "renesas,ra-cgc-pll"; + #clock-cells = <0>; + + /* PLL */ + source = ; + div = ; + mul = <20 0>; + status = "disabled"; + }; + + pclkblock: pclkblock { + compatible = "renesas,ra-cgc-pclk-block"; + #clock-cells = <0>; + sysclock-src = ; + status = "okay"; + + iclk: iclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclka: pclka { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkc: pclkc { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + bclk: bclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + bclkout: bclkout { + compatible = "renesas,ra-cgc-busclk"; + clk_out_div = <2>; + sdclk = <1>; + #clock-cells = <0>; + }; + #clock-cells = <2>; + status = "okay"; + }; + + uclk: uclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + fclk: fclk { + compatible = "renesas,ra-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + clkout: clkout { + compatible = "renesas,ra-cgc-pclk"; + #clock-cells = <2>; + status = "disabled"; + }; + }; + }; +}; diff --git a/soc/renesas/ra/ra6m2/CMakeLists.txt b/soc/renesas/ra/ra6m2/CMakeLists.txt new file mode 100644 index 00000000000..ccc5f9899ae --- /dev/null +++ b/soc/renesas/ra/ra6m2/CMakeLists.txt @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) + +zephyr_linker_sources(ROM_START opt_set_mem.ld) + +zephyr_linker_sources(SECTIONS sections.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra6m2/Kconfig b/soc/renesas/ra/ra6m2/Kconfig new file mode 100644 index 00000000000..44562acbf90 --- /dev/null +++ b/soc/renesas/ra/ra6m2/Kconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA6M2 + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_ARM_MPU + select HAS_RENESAS_RA_FSP + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select FPU + select HAS_SWO + select XIP diff --git a/soc/renesas/ra/ra6m2/Kconfig.defconfig b/soc/renesas/ra/ra6m2/Kconfig.defconfig new file mode 100644 index 00000000000..33ada2c756e --- /dev/null +++ b/soc/renesas/ra/ra6m2/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RA6M2 + +config NUM_IRQS + default 96 + +config PINCTRL + default y + +endif # SOC_SERIES_RA6M2 diff --git a/soc/renesas/ra/ra6m2/Kconfig.soc b/soc/renesas/ra/ra6m2/Kconfig.soc new file mode 100644 index 00000000000..6c8b47e20cf --- /dev/null +++ b/soc/renesas/ra/ra6m2/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA6M2 + bool + select SOC_FAMILY_RENESAS_RA + help + Renesas RA6M2 series + +config SOC_R7FA6M2AF3CFB + bool + select SOC_SERIES_RA6M2 + help + R7FA6M2AF3CFB + +config SOC_SERIES + default "ra6m2" if SOC_SERIES_RA6M2 + +config SOC + default "r7fa6m2af3cfb" if SOC_R7FA6M2AF3CFB diff --git a/soc/renesas/ra/ra6m2/opt_set_mem.ld b/soc/renesas/ra/ra6m2/opt_set_mem.ld new file mode 100644 index 00000000000..07aef9e92d8 --- /dev/null +++ b/soc/renesas/ra/ra6m2/opt_set_mem.ld @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* ROM Registers start at address 0x00000400 */ +. = 0x400; +KEEP(*(.rom_registers*)) +/* Reserving 0x100 bytes of space for ROM registers. */ +. = 0x500; diff --git a/soc/renesas/ra/ra6m2/sections.ld b/soc/renesas/ra/ra6m2/sections.ld new file mode 100644 index 00000000000..b850a64f643 --- /dev/null +++ b/soc/renesas/ra/ra6m2/sections.ld @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +.code_in_ram : +{ + . = ALIGN(4); + __Code_In_RAM_Start = .; + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; +} > RAMABLE_REGION + +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) + +SECTION_PROLOGUE(.id_code,,) +{ + KEEP(*(.id_code*)) +} GROUP_LINK_IN(ID_CODE) diff --git a/soc/renesas/ra/ra6m2/soc.c b/soc/renesas/ra/ra6m2/soc.c new file mode 100644 index 00000000000..85e5742ebfd --- /dev/null +++ b/soc/renesas/ra/ra6m2/soc.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RA6M2 family processor + */ + +#include +#include +#include +#include +#include +#include +#include +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#include "bsp_cfg.h" +#include + +uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; + +volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int renesas_ra6m2_init(void) +{ + uint32_t key; + + key = irq_lock(); + + SystemCoreClock = BSP_MOCO_HZ; + g_protect_pfswe_counter = 0; + bsp_clock_init(); + + irq_unlock(key); + + return 0; +} + +SYS_INIT(renesas_ra6m2_init, PRE_KERNEL_1, 0); diff --git a/soc/renesas/ra/ra6m2/soc.h b/soc/renesas/ra/ra6m2/soc.h new file mode 100644 index 00000000000..8ad75a1efea --- /dev/null +++ b/soc/renesas/ra/ra6m2/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Renesas RA6M2 family MCU + */ + +#ifndef ZEPHYR_SOC_RENESAS_RA6M2_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RA6M2_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RA6M2_SOC_H_ */ diff --git a/soc/renesas/ra/soc.yml b/soc/renesas/ra/soc.yml index c4656103f56..c430fdb7bfc 100644 --- a/soc/renesas/ra/soc.yml +++ b/soc/renesas/ra/soc.yml @@ -28,3 +28,6 @@ family: - name: ra6m1 socs: - name: r7fa6m1ad3cfp + - name: ra6m2 + socs: + - name: r7fa6m2af3cfb