boards: frdm_mcxw71: Enable ADC and tests/sample
Enable LPADC on the FRDM_MCXW71 and add overlays for tests and sample Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
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7 changed files with 125 additions and 0 deletions
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@ -66,6 +66,8 @@ The ``frdm_mcxw71`` board target in Zephyr currently supports the following feat
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+-----------+------------+-------------------------------------+
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| VREF | on-chip | regulator |
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+-----------+------------+-------------------------------------+
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| LPADC | on-chip | adc |
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+-----------+------------+-------------------------------------+
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Fetch Binary Blobs
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******************
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@ -58,4 +58,14 @@
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drive-strength = "low";
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};
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};
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pinmux_lpadc0: pinmux_lpadc0 {
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group0 {
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pinmux = <ADC0_A6_PTD2>,
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<ADC0_B6_PTD3>,
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<ADC0_B5_PTD1>;
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drive-strength = "low";
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slew-rate = "fast";
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};
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};
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};
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@ -131,3 +131,9 @@
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max-bitrate = <5000000>;
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};
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};
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&adc0 {
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pinctrl-0 = <&pinmux_lpadc0>;
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pinctrl-names = "default";
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status = "okay";
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};
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@ -20,3 +20,4 @@ supported:
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- i2c
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- can
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- regulator
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- adc
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29
samples/drivers/adc/adc_dt/boards/frdm_mcxw71.overlay
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29
samples/drivers/adc/adc_dt/boards/frdm_mcxw71.overlay
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@ -0,0 +1,29 @@
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/*
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* Copyright 2024 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
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/ {
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zephyr,user {
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io-channels = <&adc0 0>;
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};
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};
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&adc0 {
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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reg = <0>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_EXTERNAL1";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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zephyr,vref-mv = <1800>;
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/* channel 2 signal 6A */
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zephyr,input-positive = <MCUX_LPADC_CH2A>;
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};
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};
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29
tests/drivers/adc/adc_api/boards/frdm_mcxw71.overlay
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tests/drivers/adc/adc_api/boards/frdm_mcxw71.overlay
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@ -0,0 +1,29 @@
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/*
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* Copyright 2024 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
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/ {
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zephyr,user {
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io-channels = <&adc0 0>;
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};
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};
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&adc0 {
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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reg = <0>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_EXTERNAL1";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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zephyr,vref-mv = <1800>;
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/* channel 2 signal 6A */
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zephyr,input-positive = <MCUX_LPADC_CH2A>;
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};
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};
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48
tests/drivers/regulator/voltage/boards/frdm_mcxw71.overlay
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48
tests/drivers/regulator/voltage/boards/frdm_mcxw71.overlay
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@ -0,0 +1,48 @@
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/*
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* Copyright 2024 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
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#include <zephyr/dt-bindings/regulator/nxp_vref.h>
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/* To do this test, connect LPADC0 channel 6A(J4 pin 5) to VREF_OUT (J2 pin 3) */
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/ {
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resources: resources {
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compatible = "test-regulator-voltage";
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regulators = <&vref>;
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tolerance-microvolt = <40000>;
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set-read-delay-ms = <1>;
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adc-avg-count = <10>;
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io-channels = <&adc0 0>;
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min-microvolt = <1000000>;
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max-microvolt = <2100000>;
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};
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};
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&vref {
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regulator-initial-mode = <NXP_VREF_MODE_INTERNAL_REGULATOR>;
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};
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&adc0 {
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#address-cells = <1>;
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#size-cells = <0>;
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/* In this case, the LPADC reference source cannot be set to VREFO,
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* switch the reference source to VDD_ANA.
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*/
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voltage-ref= <0>;
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channel@0 {
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reg = <0>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_EXTERNAL0";
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zephyr,vref-mv = <3300>;
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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/* the signal name is ADC0_A6 but it is still channel 2 */
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zephyr,input-positive = <MCUX_LPADC_CH2A>;
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};
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};
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