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soc: arm: nxp_imx: rt11xx: add support for CONFIG_ETH_MCUX_RMII_EXT_CLK

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ENET_REF_CLK as an input during rt11xx clock initialization.

Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
This commit is contained in:
Peter van der Perk 2023-11-18 19:08:21 +01:00 • committed by Fabio Baltieri
commit 5edb7cbe41
2 changed files with 14 additions and 1 deletions
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3
boards/arm/vmu_rt1170/vmu_rt1170-pinctrl.dtsi
View file

@ -38,8 +38,9 @@
group3 { group3 {
pinmux = <&iomuxc_gpio_disp_b1_11_enet_1g_ref_clk1>; pinmux = <&iomuxc_gpio_disp_b1_11_enet_1g_ref_clk1>;
drive-strength = "high"; drive-strength = "high";
slew-rate = "slow"; slew-rate = "fast";
input-enable; input-enable;
bias-pull-down;
}; };
}; };

12
soc/arm/nxp_imx/rt/soc_rt11xx.c
View file

@ -402,10 +402,16 @@ static ALWAYS_INLINE void clock_init(void)
rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2; rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2;
rootCfg.div = 10; rootCfg.div = 10;
CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg); CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg);
#if CONFIG_ETH_MCUX_RMII_EXT_CLK
/* Set ENET_REF_CLK as an input driven by PHY */
IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U);
IOMUXC_GPR->GPR4 |= IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(0x1U);
#else
/* Set ENET_REF_CLK as an output driven by ENET1_CLK_ROOT */ /* Set ENET_REF_CLK as an output driven by ENET1_CLK_ROOT */
IOMUXC_GPR->GPR4 |= (IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U) | IOMUXC_GPR->GPR4 |= (IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U) |
IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(0x1U)); IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(0x1U));
#endif #endif
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet1g), okay) #if DT_NODE_HAS_STATUS(DT_NODELABEL(enet1g), okay)
/* /*
* 50 MHz clock for 10/100Mbit RMII PHY - * 50 MHz clock for 10/100Mbit RMII PHY -
@ -414,11 +420,17 @@ static ALWAYS_INLINE void clock_init(void)
rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2; rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2;
rootCfg.div = 10; rootCfg.div = 10;
CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg); CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg);
#if CONFIG_ETH_MCUX_RMII_EXT_CLK
/* Set ENET1G_REF_CLK as an input driven by PHY */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U);
IOMUXC_GPR->GPR5 |= IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(0x1U);
#else
/* Set ENET1G_REF_CLK as an output driven by ENET2_CLK_ROOT */ /* Set ENET1G_REF_CLK as an output driven by ENET2_CLK_ROOT */
IOMUXC_GPR->GPR5 |= (IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U) | IOMUXC_GPR->GPR5 |= (IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U) |
IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(0x1U)); IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(0x1U));
#endif #endif
#endif #endif
#endif
#ifdef CONFIG_PTP_CLOCK_MCUX #ifdef CONFIG_PTP_CLOCK_MCUX
/* 24MHz PTP clock */ /* 24MHz PTP clock */