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arch/x86: Generalize cache manipulation functions

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We assume that all x86 CPUs do have clflush instructions.
And the cache line size is now provided through DTS.

So detecting clflush instruction as well as the cache line size is no
longer required at runtime and thus removed.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka 2021-02-11 09:52:29 +01:00 • committed by Anas Nashif
commit 5e4e0298e9
9 changed files with 3 additions and 168 deletions
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28
arch/x86/core/Kconfig.ia32
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@ -144,34 +144,6 @@ config X86_FP_USE_SOFT_FLOAT
endmenu
config DCACHE_LINE_SIZE
default 64 if CPU_ATOM
config CLFLUSH_INSTRUCTION_SUPPORTED
bool "CLFLUSH instruction supported"
depends on !CLFLUSH_DETECT && CACHE_MANAGEMENT
help
An implementation of sys_cache_flush() that uses CLFLUSH is made
available, instead of the one using WBINVD.
This option should only be enabled if it is known in advance that the
CPU supports the CLFLUSH instruction. It disables runtime detection of
CLFLUSH support thereby reducing both memory footprint and boot time.
config CLFLUSH_DETECT
bool "Detect support of CLFLUSH instruction at runtime"
depends on CACHE_MANAGEMENT
help
This option should be enabled if it is not known in advance whether the
CPU supports the CLFLUSH instruction or not.
The CPU is queried at boot time to determine which of the multiple
implementations of sys_cache_flush() linked into the image is the
correct one to use.
If the CPU's support (or lack thereof) of CLFLUSH is known in advance, then
disable this option and set CLFLUSH_INSTRUCTION_SUPPORTED as appropriate.
config X86_DYNAMIC_IRQ_STUBS
int "Number of dynamic interrupt stubs"
depends on DYNAMIC_INTERRUPTS