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soc: nxp: imx: clang-format imx93 code files

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clang-format imx93 code files.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
This commit is contained in:
Yangbo Lu 2024-08-23 05:40:34 +02:00 • committed by Alberto Escolar
commit 5e09d7db26
2 changed files with 49 additions and 66 deletions
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46
soc/nxp/imx/imx9/imx93/a55/mmu_regions.c
View file

@ -10,57 +10,43 @@
static const struct arm_mmu_region mmu_regions[] = {
MMU_REGION_FLAT_ENTRY("GIC",
DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
MMU_REGION_FLAT_ENTRY("GIC",
DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
MMU_REGION_FLAT_ENTRY("CCM",
DT_REG_ADDR(DT_NODELABEL(ccm)),
DT_REG_SIZE(DT_NODELABEL(ccm)),
MMU_REGION_FLAT_ENTRY("CCM", DT_REG_ADDR(DT_NODELABEL(ccm)), DT_REG_SIZE(DT_NODELABEL(ccm)),
MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
MMU_REGION_FLAT_ENTRY("ANA_PLL",
DT_REG_ADDR(DT_NODELABEL(ana_pll)),
MMU_REGION_FLAT_ENTRY("ANA_PLL", DT_REG_ADDR(DT_NODELABEL(ana_pll)),
DT_REG_SIZE(DT_NODELABEL(ana_pll)),
MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
MMU_REGION_FLAT_ENTRY("IOMUXC",
DT_REG_ADDR(DT_NODELABEL(iomuxc)),
MMU_REGION_FLAT_ENTRY("IOMUXC", DT_REG_ADDR(DT_NODELABEL(iomuxc)),
DT_REG_SIZE(DT_NODELABEL(iomuxc)),
MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
MMU_REGION_DT_COMPAT_FOREACH_FLAT_ENTRY(nxp_kinetis_lpuart,
(MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS))
(MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS))
#if CONFIG_SOF
MMU_REGION_FLAT_ENTRY("MU2_A",
DT_REG_ADDR(DT_NODELABEL(mu2_a)),
DT_REG_SIZE(DT_NODELABEL(mu2_a)),
MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
MMU_REGION_FLAT_ENTRY("MU2_A", DT_REG_ADDR(DT_NODELABEL(mu2_a)),
DT_REG_SIZE(DT_NODELABEL(mu2_a)),
MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
MMU_REGION_FLAT_ENTRY("OUTBOX",
DT_REG_ADDR(DT_NODELABEL(outbox)),
DT_REG_SIZE(DT_NODELABEL(outbox)),
MT_NORMAL | MT_P_RW_U_NA | MT_NS),
MMU_REGION_FLAT_ENTRY("OUTBOX", DT_REG_ADDR(DT_NODELABEL(outbox)),
DT_REG_SIZE(DT_NODELABEL(outbox)), MT_NORMAL | MT_P_RW_U_NA | MT_NS),
MMU_REGION_FLAT_ENTRY("INBOX",
DT_REG_ADDR(DT_NODELABEL(inbox)),
DT_REG_SIZE(DT_NODELABEL(inbox)),
MT_NORMAL | MT_P_RW_U_NA | MT_NS),
MMU_REGION_FLAT_ENTRY("INBOX", DT_REG_ADDR(DT_NODELABEL(inbox)),
DT_REG_SIZE(DT_NODELABEL(inbox)), MT_NORMAL | MT_P_RW_U_NA | MT_NS),
MMU_REGION_FLAT_ENTRY("STREAM",
DT_REG_ADDR(DT_NODELABEL(stream)),
DT_REG_SIZE(DT_NODELABEL(stream)),
MT_NORMAL | MT_P_RW_U_NA | MT_NS),
MMU_REGION_FLAT_ENTRY("STREAM", DT_REG_ADDR(DT_NODELABEL(stream)),
DT_REG_SIZE(DT_NODELABEL(stream)), MT_NORMAL | MT_P_RW_U_NA | MT_NS),
MMU_REGION_FLAT_ENTRY("HOST_RAM",
DT_REG_ADDR(DT_NODELABEL(host_ram)),
MMU_REGION_FLAT_ENTRY("HOST_RAM", DT_REG_ADDR(DT_NODELABEL(host_ram)),
DT_REG_SIZE(DT_NODELABEL(host_ram)),
MT_NORMAL | MT_P_RW_U_NA | MT_NS),
#endif /* CONFIG_SOF */

69
soc/nxp/imx/imx9/imx93/pinctrl_soc.h
View file

@ -16,31 +16,30 @@ extern "C" {
#endif
#define MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC1_SW_PAD_CTL_PAD_HYS_SHIFT
#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC1_SW_PAD_CTL_PAD_OD_SHIFT
#define MCUX_IMX_BIAS_PULL_DOWN_SHIFT IOMUXC1_SW_PAD_CTL_PAD_PD_SHIFT
#define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC1_SW_PAD_CTL_PAD_PU_SHIFT
#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC1_SW_PAD_CTL_PAD_FSEL1_SHIFT
#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC1_SW_PAD_CTL_PAD_DSE_SHIFT
#define MCUX_IMX_INPUT_ENABLE_SHIFT 23 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1)
#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC1_SW_PAD_CTL_PAD_OD_SHIFT
#define MCUX_IMX_BIAS_PULL_DOWN_SHIFT IOMUXC1_SW_PAD_CTL_PAD_PD_SHIFT
#define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC1_SW_PAD_CTL_PAD_PU_SHIFT
#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC1_SW_PAD_CTL_PAD_FSEL1_SHIFT
#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC1_SW_PAD_CTL_PAD_DSE_SHIFT
#define MCUX_IMX_INPUT_ENABLE_SHIFT 23 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1)
#define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id) \
((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \
(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \
(DT_PROP(node_id, bias_pull_down) << MCUX_IMX_BIAS_PULL_DOWN_SHIFT) | \
(DT_PROP(node_id, bias_pull_up) << MCUX_IMX_BIAS_PULL_UP_SHIFT) | \
(DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \
((~(0xff << DT_ENUM_IDX(node_id, drive_strength))) << MCUX_IMX_DRIVE_STRENGTH_SHIFT) | \
#define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id) \
((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \
(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \
(DT_PROP(node_id, bias_pull_down) << MCUX_IMX_BIAS_PULL_DOWN_SHIFT) | \
(DT_PROP(node_id, bias_pull_up) << MCUX_IMX_BIAS_PULL_UP_SHIFT) | \
(DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \
((~(0xff << DT_ENUM_IDX(node_id, drive_strength))) << MCUX_IMX_DRIVE_STRENGTH_SHIFT) | \
(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT))
/* This struct must be present. It is used by the mcux gpio driver */
struct pinctrl_soc_pinmux {
uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
uint8_t mux_mode: 4; /*!< Mux value for SW_PAD_MUX register */
uint32_t input_daisy:4; /*!< Mux value for SELECT_INPUT_DAISY register */
uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
uint8_t mux_mode: 4; /*!< Mux value for SW_PAD_MUX register */
uint32_t input_daisy: 4; /*!< Mux value for SELECT_INPUT_DAISY register */
};
struct pinctrl_soc_pin {
@ -51,29 +50,27 @@ struct pinctrl_soc_pin {
typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
/* This definition must be present. It is used by the mcux gpio driver */
#define MCUX_IMX_PINMUX(node_id) \
{ \
.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \
.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \
.input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \
.mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \
.input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \
#define MCUX_IMX_PINMUX(node_id) \
{ \
.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \
.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \
.input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \
.mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \
.input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \
}
#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \
#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \
MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
{ \
.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PINCFG_INIT(group_id), \
#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
{ \
.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PINCFG_INIT(group_id), \
},
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}; \
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
Z_PINCTRL_STATE_PIN_INIT)};
#ifdef __cplusplus
}