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soc: rt10xx: Set divisor for sys pll (PLL2) PFD0

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Divisor must be set to calculate SD host controller clock frequency in
clock driver.

Fixes #42380

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2022-02-01 19:33:18 -06:00 • committed by Carles Cufí
commit 5dfd3c3786
1 changed files with 2 additions and 0 deletions
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2
soc/arm/nxp_imx/rt/soc_rt10xx.c
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@ -174,12 +174,14 @@ static ALWAYS_INLINE void clock_init(void)
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
/* Configure USDHC clock source and divider */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U);
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1U);
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U);
CLOCK_EnableClock(kCLOCK_Usdhc1);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay) && CONFIG_DISK_DRIVER_SDMMC
/* Configure USDHC clock source and divider */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U);
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1U);
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 1U);
CLOCK_EnableClock(kCLOCK_Usdhc2);