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pcie: Trivial documentation cleanup

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Cleanup PCIE documentation.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
This commit is contained in:
Andrei Emeltchenko 2020-10-14 13:57:37 +03:00 • committed by Andrew Boie
commit 5df906f06f
1 changed files with 4 additions and 4 deletions
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8
include/drivers/pcie/pcie.h
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@ -65,7 +65,7 @@ extern void pcie_conf_write(pcie_bdf_t bdf, unsigned int reg, uint32_t data);
* @brief Probe for the presence of a PCI(e) endpoint.
*
* @param bdf the endpoint to probe
* @param id the endpoint ID to expect, or PCI_ID_ANY for "any device"
* @param id the endpoint ID to expect, or PCIE_ID_NONE for "any device"
* @return true if the device is present, false otherwise
*/
extern bool pcie_probe(pcie_bdf_t bdf, pcie_id_t id);
@ -74,11 +74,11 @@ extern bool pcie_probe(pcie_bdf_t bdf, pcie_id_t id);
* @brief Get the nth MMIO address assigned to an endpoint.
* @param bdf the PCI(e) endpoint
* @param index (0-based) index
* @return the address, or PCI_CONF_BAR_NONE if nonexistent.
* @return the address, or PCIE_CONF_BAR_NONE if nonexistent.
*
* A PCI(e) endpoint has 0 or more memory-mapped regions. This function
* allows the caller to enumerate them by calling with index=0..n. If
* PCI_CONF_BAR_NONE is returned, there are no further regions. The indices
* PCIE_CONF_BAR_NONE is returned, there are no further regions. The indices
* are order-preserving with respect to the endpoint BARs: e.g., index 0
* will return the lowest-numbered memory BAR on the endpoint.
*/
@ -109,7 +109,7 @@ extern unsigned int pcie_wired_irq(pcie_bdf_t bdf);
*
* If MSI is enabled and the endpoint supports it, the endpoint will
* be configured to generate the specified IRQ via MSI. Otherwise, it
* is assumed that the IRQ IRQ has been routed by the boot firmware
* is assumed that the IRQ has been routed by the boot firmware
* to the specified IRQ, and the IRQ is enabled (at the I/O APIC, or
* wherever appropriate).
*/