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drivers: STM32: Rework CLK48 HSEM protection

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Due to HSEM implementation #24862, USB CLK48 lock implementation
#25850 should be reworked.
And by the way, implement the same in entropy which is using the
same clock.

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
This commit is contained in:
Alexandre Bourdiol 2020-07-08 11:18:07 +02:00 • committed by Carles Cufí
commit 5deb8ffe0c
2 changed files with 23 additions and 7 deletions
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10
drivers/entropy/entropy_stm32.c
View file

@ -21,6 +21,7 @@
#include <sys/printk.h>
#include <drivers/clock_control.h>
#include <drivers/clock_control/stm32_clock_control.h>
#include "stm32_hsem.h"
#define IRQN DT_INST_IRQN(0)
#define IRQ_PRIO DT_INST_IRQ(0, priority)
@ -386,6 +387,7 @@ static int entropy_stm32_rng_init(const struct device *dev)
LL_SYSCFG_VREFINT_EnableHSI48();
#endif /* CONFIG_SOC_SERIES_STM32L0X */
z_stm32_hsem_lock(CFG_HW_CLK48_CONFIG_SEMID, HSEM_LOCK_DEFAULT_RETRY);
/* Use the HSI48 for the RNG */
LL_RCC_HSI48_Enable();
while (!LL_RCC_HSI48_IsReady()) {
@ -393,6 +395,14 @@ static int entropy_stm32_rng_init(const struct device *dev)
}
LL_RCC_SetRNGClockSource(LL_RCC_RNG_CLKSOURCE_HSI48);
#if !defined(CONFIG_SOC_SERIES_STM32WBX)
/* Specially for STM32WB, don't unlock the HSEM to prevent M0 core
* to disable HSI48 clock used for RNG.
*/
z_stm32_hsem_unlock(CFG_HW_CLK48_CONFIG_SEMID);
#endif /* CONFIG_SOC_SERIES_STM32WBX */
#endif /* CONFIG_SOC_SERIES_STM32L4X */
dev_data->clock = device_get_binding(STM32_CLOCK_CONTROL_NAME);

20
drivers/usb/device/usb_dc_stm32.c
View file

@ -52,6 +52,7 @@
#include <drivers/clock_control/stm32_clock_control.h>
#include <sys/util.h>
#include <drivers/gpio.h>
#include "stm32_hsem.h"
#define LOG_LEVEL CONFIG_USB_DRIVER_LOG_LEVEL
#include <logging/log.h>
@ -110,8 +111,6 @@ LOG_MODULE_REGISTER(usb_dc_stm32);
*/
#ifdef USB
#define CFG_HW_RCC_CRRCR_CCIPR_SEMID 5
#define EP0_MPS 64U
#define EP_MPS 64U
@ -251,10 +250,7 @@ static int usb_dc_stm32_clock_enable(void)
}
#endif /* CONFIG_SOC_SERIES_STM32L0X */
#ifdef CONFIG_SOC_SERIES_STM32WBX
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_CRRCR_CCIPR_SEMID)) {
}
#endif /* CONFIG_SOC_SERIES_STM32WBX */
z_stm32_hsem_lock(CFG_HW_CLK48_CONFIG_SEMID, HSEM_LOCK_DEFAULT_RETRY);
LL_RCC_HSI48_Enable();
while (!LL_RCC_HSI48_IsReady()) {
@ -262,6 +258,14 @@ static int usb_dc_stm32_clock_enable(void)
}
LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_HSI48);
#if !defined(CONFIG_SOC_SERIES_STM32WBX)
/* Specially for STM32WB, don't unlock the HSEM to prevent M0 core
* to disable HSI48 clock used for RNG.
*/
z_stm32_hsem_unlock(CFG_HW_CLK48_CONFIG_SEMID);
#endif /* CONFIG_SOC_SERIES_STM32WBX */
#elif defined(LL_RCC_USB_CLKSOURCE_NONE)
/* When MSI is configured in PLL mode with a 32.768 kHz clock source,
* the MSI frequency can be automatically trimmed by hardware to reach
@ -913,7 +917,9 @@ int usb_dc_detach(void)
LOG_ERR("Not implemented");
#ifdef CONFIG_SOC_SERIES_STM32WBX
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_CRRCR_CCIPR_SEMID, 0);
/* Specially for STM32WB, unlock the HSEM when USB is no more used. */
z_stm32_hsem_unlock(CFG_HW_CLK48_CONFIG_SEMID);
/*
* TODO: AN5289 notes a process of locking Sem0, with possible waits
* via interrupts before switching off CLK48, but lacking any actual