boards: riscv: neorv32: Updates compatibility to neoverse v1.8.6
With NEORV32 v1.8.2 the UART module was changed to a simpler implementation. This updates the UART driver for the open-source NEORV32 RISC-V compatible processor system (SOC). Signed-off-by: Tim-Marek Thomas <thomas@sra.uni-hannover.de>
This commit is contained in:
Tim-Marek Thomas
Fabio Baltieri
parent
c16647d02a
commit
5d75940ae3
6 changed files with 33 additions and 59 deletions
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@ -16,6 +16,8 @@ For more information about the NEORV32, see the following websites:
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- `The NEORV32 RISC-V Processor Datasheet`_
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- `The NEORV32 RISC-V Processor User Guide`_
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The currently supported version is 1.8.6.
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Supported Features
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==================
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@ -1,4 +1,4 @@
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# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SOC_NEORV32_V1_6_1=y
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CONFIG_SOC_NEORV32_V1_8_6=y
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@ -3,5 +3,5 @@
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board_check_revision(
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FORMAT MAJOR.MINOR.PATCH
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DEFAULT_REVISION 1.6.1
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DEFAULT_REVISION 1.8.6
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)
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@ -21,24 +21,27 @@ LOG_MODULE_REGISTER(uart_neorv32, CONFIG_UART_LOG_LEVEL);
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#define NEORV32_UART_DATA_OFFSET 0x04
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/* UART_CTRL register bits */
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#define NEORV32_UART_CTRL_BAUD_MASK BIT_MASK(12)
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#define NEORV32_UART_CTRL_BAUD_POS 0U
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#define NEORV32_UART_CTRL_EN BIT(0)
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#define NEORV32_UART_CTRL_SIM_MODE BIT(1)
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#define NEORV32_UART_CTRL_HWFC_EN BIT(2)
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#define NEORV32_UART_CTRL_PRSC_POS 3U
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#define NEORV32_UART_CTRL_PRSC_MASK BIT_MASK(3)
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#define NEORV32_UART_CTRL_PRSC_POS 24U
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#define NEORV32_UART_CTRL_RTS_EN BIT(20)
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#define NEORV32_UART_CTRL_CTS_EN BIT(21)
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#define NEORV32_UART_CTRL_PMODE_NONE BIT(22)
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#define NEORV32_UART_CTRL_PMODE_EVEN BIT(23)
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#define NEORV32_UART_CTRL_PMODE_ODD (BIT(22) | BIT(23))
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#define NEORV32_UART_CTRL_EN BIT(28)
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#define NEORV32_UART_CTRL_BAUD_POS 6U
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#define NEORV32_UART_CTRL_BAUD_MASK BIT_MASK(10)
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#define NEORV32_UART_CTRL_RX_NEMPTY BIT(16)
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#define NEORV32_UART_CTRL_RX_HALF BIT(17)
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#define NEORV32_UART_CTRL_RX_FULL BIT(18)
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#define NEORV32_UART_CTRL_TX_NEMPTY BIT(19)
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#define NEORV32_UART_CTRL_TX_HALF BIT(20)
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#define NEORV32_UART_CTRL_TX_FULL BIT(21)
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#define NEORV32_UART_CTRL_IRQ_RX_NEMPTY BIT(22)
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#define NEORV32_UART_CTRL_IRQ_RX_HALF BIT(23)
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#define NEORV32_UART_CTRL_IRQ_RX_FULL BIT(24)
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#define NEORV32_UART_CTRL_IRQ_TX_EMPTY BIT(25)
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#define NEORV32_UART_CTRL_IRQ_TX_NHALF BIT(26)
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#define NEORV32_UART_CTRL_RX_OVER BIT(30)
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#define NEORV32_UART_CTRL_TX_BUSY BIT(31)
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/* UART_DATA register status bits */
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#define NEORV32_UART_DATA_PERR BIT(28)
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#define NEORV32_UART_DATA_FERR BIT(29)
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#define NEORV32_UART_DATA_OVERR BIT(30)
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#define NEORV32_UART_DATA_AVAIL BIT(31)
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struct neorv32_uart_config {
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const struct device *syscon;
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uint32_t feature_mask;
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@ -100,7 +103,7 @@ static int neorv32_uart_poll_in(const struct device *dev, unsigned char *c)
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data = neorv32_uart_read_data(dev);
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if ((data & NEORV32_UART_DATA_AVAIL) != 0) {
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if ((data & NEORV32_UART_CTRL_RX_NEMPTY) != 0) {
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*c = data & BIT_MASK(8);
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return 0;
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}
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@ -116,29 +119,6 @@ static void neorv32_uart_poll_out(const struct device *dev, unsigned char c)
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neorv32_uart_write_data(dev, c);
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}
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static int neorv32_uart_err_check(const struct device *dev)
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{
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struct neorv32_uart_data *data = dev->data;
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int err = 0;
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if ((data->last_data & NEORV32_UART_DATA_OVERR) != 0) {
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err |= UART_ERROR_OVERRUN;
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}
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if ((data->last_data & NEORV32_UART_DATA_PERR) != 0) {
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err |= UART_ERROR_PARITY;
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}
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if ((data->last_data & NEORV32_UART_DATA_FERR) != 0) {
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err |= UART_ERROR_FRAMING;
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}
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data->last_data &= ~(NEORV32_UART_DATA_OVERR | NEORV32_UART_DATA_PERR |
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NEORV32_UART_DATA_FERR);
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return err;
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}
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static int neorv32_uart_configure(const struct device *dev, const struct uart_config *cfg)
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{
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const struct neorv32_uart_config *config = dev->config;
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@ -163,13 +143,6 @@ static int neorv32_uart_configure(const struct device *dev, const struct uart_co
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switch (cfg->parity) {
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case UART_CFG_PARITY_NONE:
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ctrl |= NEORV32_UART_CTRL_PMODE_NONE;
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break;
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case UART_CFG_PARITY_ODD:
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ctrl |= NEORV32_UART_CTRL_PMODE_ODD;
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break;
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case UART_CFG_PARITY_EVEN:
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ctrl |= NEORV32_UART_CTRL_PMODE_EVEN;
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break;
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default:
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LOG_ERR("unsupported parity mode %d", cfg->parity);
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@ -181,7 +154,7 @@ static int neorv32_uart_configure(const struct device *dev, const struct uart_co
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ctrl |= 0;
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break;
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case UART_CFG_FLOW_CTRL_RTS_CTS:
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ctrl |= NEORV32_UART_CTRL_RTS_EN | NEORV32_UART_CTRL_CTS_EN;
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ctrl |= NEORV32_UART_CTRL_HWFC_EN;
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break;
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default:
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LOG_ERR("unsupported flow control mode %d", cfg->flow_ctrl);
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@ -270,9 +243,9 @@ static int neorv32_uart_fifo_read(const struct device *dev, uint8_t *rx_data, co
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__ASSERT_NO_MSG(rx_data != NULL);
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while ((data->last_data & NEORV32_UART_DATA_AVAIL) != 0) {
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while ((data->last_data & NEORV32_UART_CTRL_RX_NEMPTY) != 0) {
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rx_data[count++] = data->last_data & BIT_MASK(8);
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data->last_data &= ~(NEORV32_UART_DATA_AVAIL);
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data->last_data &= ~(NEORV32_UART_CTRL_RX_NEMPTY);
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if (count >= size) {
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break;
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@ -367,7 +340,7 @@ static int neorv32_uart_irq_rx_ready(const struct device *dev)
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return 0;
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}
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return (data->last_data & NEORV32_UART_DATA_AVAIL) != 0;
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return (data->last_data & NEORV32_UART_CTRL_RX_NEMPTY) != 0;
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}
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static int neorv32_uart_irq_is_pending(const struct device *dev)
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@ -467,7 +440,6 @@ static int neorv32_uart_pm_action(const struct device *dev,
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static const struct uart_driver_api neorv32_uart_driver_api = {
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.poll_in = neorv32_uart_poll_in,
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.poll_out = neorv32_uart_poll_out,
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.err_check = neorv32_uart_err_check,
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.configure = neorv32_uart_configure,
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.config_get = neorv32_uart_config_get,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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@ -5,8 +5,8 @@ choice
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prompt "NEORV32 Version"
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depends on SOC_SERIES_NEORV32
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config SOC_NEORV32_V1_6_1
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bool "v1.6.1"
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config SOC_NEORV32_V1_8_6
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bool "v1.8.6"
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# NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO
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select ATOMIC_OPERATIONS_C
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@ -16,7 +16,7 @@ if SOC_SERIES_NEORV32
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config SOC_NEORV32_VERSION
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hex
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default 0x01060100 if SOC_NEORV32_V1_6_1
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default 0x01080600 if SOC_NEORV32_V1_8_6
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help
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The targeted NEORV32 version as BCD-coded number. The format is
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identical to that of the NEORV32 Machine implementation ID (mimpid)
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@ -26,7 +26,7 @@ SECTION_FUNC(reset, __reset)
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#endif /* CONFIG_USERSPACE */
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/* Allow mcycle and minstret counters to increment */
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li x11, ~5
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li x11, ~2
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csrw mcountinhibit, x11
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/* Zerorize counters */
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