soc: nxp: imx: add i.MX95 Cortex-A55 support

Added basic soc support for i.MX95 Cortex-A55.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

soc/nxp/imx/imx9/imx95/CMakeLists.txt

@@ -4,4 +4,6 @@ zephyr_include_directories(.)
 
 if(${CONFIG_MCUX_CORE_SUFFIX} STREQUAL "_cm7")
   add_subdirectory(m7)
+elseif(${CONFIG_MCUX_CORE_SUFFIX} STREQUAL "_ca55")
+  add_subdirectory(a55)
 endif()

soc/nxp/imx/imx9/imx95/Kconfig

@@ -12,5 +12,12 @@ config SOC_MIMX9596_M7
 	select ARM_MPU
 	select HAS_MCUX
 
+config SOC_MIMX9596_A55
+	select ARM64
+	select CPU_CORTEX_A55
+	select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
+	select HAS_MCUX
+
 config MCUX_CORE_SUFFIX
 	default "_cm7" if SOC_MIMX9596_M7
+	default "_ca55" if SOC_MIMX9596_A55

soc/nxp/imx/imx9/imx95/Kconfig.defconfig.mimx95.a55

@@ -0,0 +1,23 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MIMX9596_A55
+
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_Z_FLASH := zephyr,flash
+
+config FLASH_SIZE
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+config FLASH_BASE_ADDRESS
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+config NUM_IRQS
+	int
+	default 320
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 24000000
+
+endif

soc/nxp/imx/imx9/imx95/Kconfig.soc

@@ -11,6 +11,12 @@ config SOC_MIMX9596_M7
 	help
 	  NXP i.MX95 M7
 
+config SOC_MIMX9596_A55
+	bool
+	select SOC_MIMX9596
+	help
+	  NXP i.MX95 A55
+
 config SOC
 	default "mimx9596" if SOC_MIMX9596
 

soc/nxp/imx/imx9/imx95/a55/CMakeLists.txt

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")

soc/nxp/imx/imx9/imx95/a55/mmu_regions.c

@@ -0,0 +1,32 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm64/arm_mmu.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/util.h>
+
+static const struct arm_mmu_region mmu_regions[] = {
+
+	MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
+			      DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
+
+	MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
+			      DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
+
+	MMU_REGION_DT_COMPAT_FOREACH_FLAT_ENTRY(nxp_mbox_imx_mu,
+						(MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS))
+
+		MMU_REGION_DT_COMPAT_FOREACH_FLAT_ENTRY(nxp_kinetis_lpuart,
+							(MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS))
+
+};
+
+const struct arm_mmu_config mmu_config = {
+	.num_regions = ARRAY_SIZE(mmu_regions),
+	.mmu_regions = mmu_regions,
+};

soc/nxp/imx/imx9/imx95/a55/soc.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_NXP_IMX_IMX95_A55_SOC_H_
+#define _SOC_NXP_IMX_IMX95_A55_SOC_H_
+
+#include <fsl_device_registers.h>
+
+#endif /* _SOC_NXP_IMX_IMX95_A55_SOC_H_ */

soc/nxp/imx/soc.yml

@@ -50,6 +50,7 @@ family:
       - name: m33
     - name: mimx9596
       cpuclusters:
+      - name: a55
       - name: m7
   - name: imx6sx
     socs: