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dts: riscv: Add sifive,plic-1.0.0 binding and fix riscv,ndev values

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Add a new sifive,plic-1.0.0 binding that inherits from the riscv,plic0
binding. The new binding adds a required riscv,ndev property, which
gives the number of external interrupts supported.

Use the new binding for microsemi-miv.dtsi (with a value of 31 for
riscv,ndev, from http://www.actel.com/ipdocs/MiV_RV32IMAF_L1_AHB_HB.pdf)
and riscv32-fe310.dtsi (which already assigns riscv,ndev).

Also remove a spurious riscv,ndev assignment from
riscv32-litex-vexriscv.dtsi.

Also make edtlib and the old scripts/dts/ scripts replace '.' in
compatible strings with '_' when generating identifiers.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This commit is contained in:
Ulf Magnusson 2019-08-01 18:14:52 +02:00 • committed by Carles Cufí
commit 5d0db517b9
9 changed files with 37 additions and 20 deletions
Download patch file Download diff file Expand all files Collapse all files

20
drivers/interrupt_controller/plic.c
View file

@ -42,7 +42,7 @@ void riscv_plic_irq_enable(u32_t irq)
u32_t key; u32_t key;
u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ; u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;
volatile u32_t *en = volatile u32_t *en =
(volatile u32_t *)DT_INST_0_RISCV_PLIC0_IRQ_EN_BASE_ADDRESS; (volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS;
key = irq_lock(); key = irq_lock();
en += (plic_irq >> 5); en += (plic_irq >> 5);
@ -68,7 +68,7 @@ void riscv_plic_irq_disable(u32_t irq)
u32_t key; u32_t key;
u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ; u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;
volatile u32_t *en = volatile u32_t *en =
(volatile u32_t *)DT_INST_0_RISCV_PLIC0_IRQ_EN_BASE_ADDRESS; (volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS;
key = irq_lock(); key = irq_lock();
en += (plic_irq >> 5); en += (plic_irq >> 5);
@ -88,7 +88,7 @@ void riscv_plic_irq_disable(u32_t irq)
int riscv_plic_irq_is_enabled(u32_t irq) int riscv_plic_irq_is_enabled(u32_t irq)
{ {
volatile u32_t *en = volatile u32_t *en =
(volatile u32_t *)DT_INST_0_RISCV_PLIC0_IRQ_EN_BASE_ADDRESS; (volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS;
u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ; u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;
en += (plic_irq >> 5); en += (plic_irq >> 5);
@ -109,14 +109,14 @@ int riscv_plic_irq_is_enabled(u32_t irq)
void riscv_plic_set_priority(u32_t irq, u32_t priority) void riscv_plic_set_priority(u32_t irq, u32_t priority)
{ {
volatile u32_t *prio = volatile u32_t *prio =
(volatile u32_t *)DT_INST_0_RISCV_PLIC0_PRIO_BASE_ADDRESS; (volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_PRIO_BASE_ADDRESS;
/* Can set priority only for PLIC-specific interrupt line */ /* Can set priority only for PLIC-specific interrupt line */
if (irq <= RISCV_MAX_GENERIC_IRQ) if (irq <= RISCV_MAX_GENERIC_IRQ)
return; return;
if (priority > DT_INST_0_RISCV_PLIC0_RISCV_MAX_PRIORITY) if (priority > DT_INST_0_SIFIVE_PLIC_1_0_0_RISCV_MAX_PRIORITY)
priority = DT_INST_0_RISCV_PLIC0_RISCV_MAX_PRIORITY; priority = DT_INST_0_SIFIVE_PLIC_1_0_0_RISCV_MAX_PRIORITY;
prio += (irq - RISCV_MAX_GENERIC_IRQ); prio += (irq - RISCV_MAX_GENERIC_IRQ);
*prio = priority; *prio = priority;
@ -140,7 +140,7 @@ int riscv_plic_get_irq(void)
static void plic_irq_handler(void *arg) static void plic_irq_handler(void *arg)
{ {
volatile struct plic_regs_t *regs = volatile struct plic_regs_t *regs =
(volatile struct plic_regs_t *) DT_INST_0_RISCV_PLIC0_REG_BASE_ADDRESS; (volatile struct plic_regs_t *) DT_INST_0_SIFIVE_PLIC_1_0_0_REG_BASE_ADDRESS;
u32_t irq; u32_t irq;
struct _isr_table_entry *ite; struct _isr_table_entry *ite;
@ -186,11 +186,11 @@ static int plic_init(struct device *dev)
ARG_UNUSED(dev); ARG_UNUSED(dev);
volatile u32_t *en = volatile u32_t *en =
(volatile u32_t *)DT_INST_0_RISCV_PLIC0_IRQ_EN_BASE_ADDRESS; (volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS;
volatile u32_t *prio = volatile u32_t *prio =
(volatile u32_t *)DT_INST_0_RISCV_PLIC0_PRIO_BASE_ADDRESS; (volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_PRIO_BASE_ADDRESS;
volatile struct plic_regs_t *regs = volatile struct plic_regs_t *regs =
(volatile struct plic_regs_t *)DT_INST_0_RISCV_PLIC0_REG_BASE_ADDRESS; (volatile struct plic_regs_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_REG_BASE_ADDRESS;
int i; int i;
/* Ensure that all interrupts are disabled initially */ /* Ensure that all interrupts are disabled initially */

3
dts/bindings/interrupt-controller/riscv,plic0.yaml
View file

@ -13,9 +13,6 @@ inherits:
!include base.yaml !include base.yaml
properties: properties:
compatible:
constraint: "riscv,plic0"
reg: reg:
category: required category: required

18
dts/bindings/interrupt-controller/sifive,plic-1.0.0.yaml Normal file
View file

@ -0,0 +1,18 @@
# Copyright (c) 2018, SiFive Inc.
#
# SPDX-License-Identifier: Apache-2.0
title: SiFive PLIC
description: SiFive RISCV-V platform-local interrupt controller
inherits:
!include riscv,plic0.yaml
properties:
compatible:
constraint: "sifive,plic-1.0.0"
riscv,ndev:
type: int
description: Number of external interrupts supported
category: required

3
dts/riscv32/microsemi-miv.dtsi
View file

@ -44,7 +44,7 @@
plic: interrupt-controller@40000000 { plic: interrupt-controller@40000000 {
#interrupt-cells = <1>; #interrupt-cells = <1>;
compatible = "riscv,plic0"; compatible = "sifive,plic-1.0.0";
interrupt-controller; interrupt-controller;
interrupts-extended = <&hlic 11>; interrupts-extended = <&hlic 11>;
reg = <0x40000000 0x2000 reg = <0x40000000 0x2000
@ -52,6 +52,7 @@
0x40200000 0x2000000>; 0x40200000 0x2000000>;
reg-names = "prio", "irq_en", "reg"; reg-names = "prio", "irq_en", "reg";
riscv,max-priority = <1>; riscv,max-priority = <1>;
riscv,ndev = <31>;
}; };
uart0: uart@70001000 { uart0: uart@70001000 {

2
dts/riscv32/riscv32-fe310.dtsi
View file

@ -91,7 +91,7 @@
}; };
plic: interrupt-controller@c000000 { plic: interrupt-controller@c000000 {
#interrupt-cells = <1>; #interrupt-cells = <1>;
compatible = "riscv,plic0"; compatible = "sifive,plic-1.0.0";
interrupt-controller; interrupt-controller;
interrupts-extended = <&hlic 11>; interrupts-extended = <&hlic 11>;
reg = <0xc000000 0x2000 reg = <0xc000000 0x2000

1
dts/riscv32/riscv32-litex-vexriscv.dtsi
View file

@ -34,7 +34,6 @@
reg = <0xbc0 0x4 0xfc0 0x4>; reg = <0xbc0 0x4 0xfc0 0x4>;
reg-names = "irq_mask", "irq_pending"; reg-names = "irq_mask", "irq_pending";
riscv,max-priority = <7>; riscv,max-priority = <7>;
riscv,ndev = <52>;
}; };
uart0: serial@e0001800 { uart0: serial@e0001800 {
compatible = "litex,uart0"; compatible = "litex,uart0";

1
scripts/dts/extract/globals.py
View file

@ -51,6 +51,7 @@ def str_to_label(s):
.replace(',', '_') \ .replace(',', '_') \
.replace('@', '_') \ .replace('@', '_') \
.replace('/', '_') \ .replace('/', '_') \
.replace('.', '_') \
.replace('+', 'PLUS') \ .replace('+', 'PLUS') \
.upper() .upper()

1
scripts/dts/gen_defines.py
View file

@ -524,6 +524,7 @@ def str2ident(s):
.replace(",", "_") \ .replace(",", "_") \
.replace("@", "_") \ .replace("@", "_") \
.replace("/", "_") \ .replace("/", "_") \
.replace(".", "_") \
.replace("+", "PLUS") \ .replace("+", "PLUS") \
.upper() .upper()

8
soc/riscv32/riscv-privilege/miv/dts_fixup.h
View file

@ -3,13 +3,13 @@
/* PLIC */ /* PLIC */
#define DT_PLIC_MAX_PRIORITY \ #define DT_PLIC_MAX_PRIORITY \
DT_RISCV_PLIC0_40000000_RISCV_MAX_PRIORITY DT_SIFIVE_PLIC_1_0_0_40000000_RISCV_MAX_PRIORITY
#define DT_PLIC_PRIO_BASE_ADDR \ #define DT_PLIC_PRIO_BASE_ADDR \
DT_RISCV_PLIC0_40000000_PRIO_BASE_ADDRESS DT_SIFIVE_PLIC_1_0_0_40000000_PRIO_BASE_ADDRESS
#define DT_PLIC_IRQ_EN_BASE_ADDR \ #define DT_PLIC_IRQ_EN_BASE_ADDR \
DT_RISCV_PLIC0_40000000_IRQ_EN_BASE_ADDRESS DT_SIFIVE_PLIC_1_0_0_40000000_IRQ_EN_BASE_ADDRESS
#define DT_PLIC_REG_BASE_ADDR \ #define DT_PLIC_REG_BASE_ADDR \
DT_RISCV_PLIC0_40000000_REG_BASE_ADDRESS DT_SIFIVE_PLIC_1_0_0_40000000_REG_BASE_ADDRESS
/* UART 0 */ /* UART 0 */
#define DT_MIV_UART_0_BASE_ADDR DT_MICROSEMI_COREUART_70001000_BASE_ADDRESS #define DT_MIV_UART_0_BASE_ADDR DT_MICROSEMI_COREUART_70001000_BASE_ADDRESS