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dts: riscv: Add sifive,plic-1.0.0 binding and fix riscv,ndev values

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Add a new sifive,plic-1.0.0 binding that inherits from the riscv,plic0
binding. The new binding adds a required riscv,ndev property, which
gives the number of external interrupts supported.

Use the new binding for microsemi-miv.dtsi (with a value of 31 for
riscv,ndev, from http://www.actel.com/ipdocs/MiV_RV32IMAF_L1_AHB_HB.pdf)
and riscv32-fe310.dtsi (which already assigns riscv,ndev).

Also remove a spurious riscv,ndev assignment from
riscv32-litex-vexriscv.dtsi.

Also make edtlib and the old scripts/dts/ scripts replace '.' in
compatible strings with '_' when generating identifiers.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This commit is contained in:
Ulf Magnusson 2019-08-01 18:14:52 +02:00 • committed by Carles Cufí
commit 5d0db517b9
9 changed files with 37 additions and 20 deletions
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20
drivers/interrupt_controller/plic.c
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@ -42,7 +42,7 @@ void riscv_plic_irq_enable(u32_t irq)
u32_t key;
u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;
volatile u32_t *en =
(volatile u32_t *)DT_INST_0_RISCV_PLIC0_IRQ_EN_BASE_ADDRESS;
(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS;
key = irq_lock();
en += (plic_irq >> 5);
@ -68,7 +68,7 @@ void riscv_plic_irq_disable(u32_t irq)
u32_t key;
u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;
volatile u32_t *en =
(volatile u32_t *)DT_INST_0_RISCV_PLIC0_IRQ_EN_BASE_ADDRESS;
(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS;
key = irq_lock();
en += (plic_irq >> 5);
@ -88,7 +88,7 @@ void riscv_plic_irq_disable(u32_t irq)
int riscv_plic_irq_is_enabled(u32_t irq)
{
volatile u32_t *en =
(volatile u32_t *)DT_INST_0_RISCV_PLIC0_IRQ_EN_BASE_ADDRESS;
(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS;
u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;
en += (plic_irq >> 5);
@ -109,14 +109,14 @@ int riscv_plic_irq_is_enabled(u32_t irq)
void riscv_plic_set_priority(u32_t irq, u32_t priority)
{
volatile u32_t *prio =
(volatile u32_t *)DT_INST_0_RISCV_PLIC0_PRIO_BASE_ADDRESS;
(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_PRIO_BASE_ADDRESS;
/* Can set priority only for PLIC-specific interrupt line */
if (irq <= RISCV_MAX_GENERIC_IRQ)
return;
if (priority > DT_INST_0_RISCV_PLIC0_RISCV_MAX_PRIORITY)
priority = DT_INST_0_RISCV_PLIC0_RISCV_MAX_PRIORITY;
if (priority > DT_INST_0_SIFIVE_PLIC_1_0_0_RISCV_MAX_PRIORITY)
priority = DT_INST_0_SIFIVE_PLIC_1_0_0_RISCV_MAX_PRIORITY;
prio += (irq - RISCV_MAX_GENERIC_IRQ);
*prio = priority;
@ -140,7 +140,7 @@ int riscv_plic_get_irq(void)
static void plic_irq_handler(void *arg)
{
volatile struct plic_regs_t *regs =
(volatile struct plic_regs_t *) DT_INST_0_RISCV_PLIC0_REG_BASE_ADDRESS;
(volatile struct plic_regs_t *) DT_INST_0_SIFIVE_PLIC_1_0_0_REG_BASE_ADDRESS;
u32_t irq;
struct _isr_table_entry *ite;
@ -186,11 +186,11 @@ static int plic_init(struct device *dev)
ARG_UNUSED(dev);
volatile u32_t *en =
(volatile u32_t *)DT_INST_0_RISCV_PLIC0_IRQ_EN_BASE_ADDRESS;
(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS;
volatile u32_t *prio =
(volatile u32_t *)DT_INST_0_RISCV_PLIC0_PRIO_BASE_ADDRESS;
(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_PRIO_BASE_ADDRESS;
volatile struct plic_regs_t *regs =
(volatile struct plic_regs_t *)DT_INST_0_RISCV_PLIC0_REG_BASE_ADDRESS;
(volatile struct plic_regs_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_REG_BASE_ADDRESS;
int i;
/* Ensure that all interrupts are disabled initially */