tests: fix various test ids and use existing scheme

Fix IDs and match them to what we have in the MAINTAINERS file.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2025-04-02 04:20:20 -04:00 committed by Benjamin Cabé
commit 5c8cf1c18c
9 changed files with 30 additions and 30 deletions

View file

@ -1,7 +1,7 @@
common:
tags: linker
tests:
application_development.code_relocation:
buildsystem.app_dev.code_relocation:
filter: not CONFIG_CPU_HAS_NXP_SYSMPU and CONFIG_MINIMAL_LIBC and
dt_chosen_enabled("zephyr,itcm")
arch_allow: arm
@ -9,14 +9,14 @@ tests:
- CONFIG_RELOCATE_TO_ITCM=y
platform_allow:
- mimxrt1060_evk/mimxrt1062/qspi
application_development.code_relocation_kinetis:
buildsystem.app_dev.code_relocation_kinetis:
filter: CONFIG_CPU_HAS_NXP_SYSMPU
arch_allow: arm
extra_configs:
- CONFIG_MPU_ALLOW_FLASH_WRITE=y
platform_allow:
- frdm_k64f
application_development.code_relocation.no_itcm:
buildsystem.app_dev.code_relocation.no_itcm:
filter: not CONFIG_CPU_HAS_NXP_SYSMPU and not dt_chosen_enabled("zephyr,itcm")
arch_allow: arm
extra_sections:
@ -31,11 +31,11 @@ tests:
- sam_e70_xplained/same70q21
integration_platforms:
- qemu_cortex_m3
application_development.code_relocation.riscv:
buildsystem.app_dev.code_relocation.riscv:
extra_args: CONF_FILE="prj_riscv.conf"
platform_allow:
- qemu_riscv32
- qemu_riscv64
application_development.code_relocation.xtensa:
buildsystem.app_dev.code_relocation.xtensa:
extra_args: CONF_FILE="prj_xtensa.conf"
platform_allow: qemu_xtensa/dc233c

View file

@ -5,4 +5,4 @@ common:
- native_sim
harness: ctest
tests:
sbom.spdx: {}
buildsystem.sbom.spdx: {}