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ARC: hsdk: openocd: replace depricated syntax

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Replace depricated openocd syntax with proper one

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
This commit is contained in:
Evgeniy Paltsev 2023-01-19 15:25:04 +00:00 • committed by Lauren Murphy
commit 5c1d311ba0
1 changed files with 13 additions and 13 deletions
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26
boards/arc/hsdk/support/openocd.cfg
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@ -10,12 +10,12 @@ adapter driver ftdi
# Only specify FTDI serial number if it is specified via # Only specify FTDI serial number if it is specified via
# "set _ZEPHYR_BOARD_SERIAL 12345" before reading this script # "set _ZEPHYR_BOARD_SERIAL 12345" before reading this script
if { [info exists _ZEPHYR_BOARD_SERIAL] } { if { [info exists _ZEPHYR_BOARD_SERIAL] } {
ftdi_serial $_ZEPHYR_BOARD_SERIAL adapter serial $_ZEPHYR_BOARD_SERIAL
} }
ftdi_vid_pid 0x0403 0x6010 ftdi vid_pid 0x0403 0x6010
ftdi_layout_init 0x0088 0x008b ftdi layout_init 0x0088 0x008b
ftdi_channel 1 ftdi channel 1
adapter speed 10000 adapter speed 10000
@ -33,7 +33,7 @@ transport select jtag
source [find cpu/arc/hs.tcl] source [find cpu/arc/hs.tcl]
set _coreid 0 set _coreid 0
set _dbgbase [expr 0x00000000 | ($_coreid << 13)] set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
# CHIPNAME will be used to choose core family (600, 700 or EM). As far as # CHIPNAME will be used to choose core family (600, 700 or EM). As far as
# OpenOCD is concerned EM and HS are identical. # OpenOCD is concerned EM and HS are identical.
@ -58,8 +58,8 @@ target create $_TARGETNAME2 arcv2 -chain-position $_TARGETNAME2
$_TARGETNAME2 configure -coreid $_coreid $_TARGETNAME2 configure -coreid $_coreid
$_TARGETNAME2 configure -dbgbase $_dbgbase $_TARGETNAME2 configure -dbgbase $_dbgbase
$_TARGETNAME2 configure -event reset-assert "arc_common_reset $_TARGETNAME2" $_TARGETNAME2 configure -event reset-assert "arc_common_reset $_TARGETNAME2"
set _coreid [expr $_coreid + 1] set _coreid [expr {$_coreid + 1}]
set _dbgbase [expr 0x00000000 | ($_coreid << 13)] set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
arc_hs_init_regs arc_hs_init_regs
# Enable L2 cache support for core 2. # Enable L2 cache support for core 2.
@ -73,8 +73,8 @@ target create $_TARGETNAME3 arcv2 -chain-position $_TARGETNAME3
$_TARGETNAME3 configure -coreid $_coreid $_TARGETNAME3 configure -coreid $_coreid
$_TARGETNAME3 configure -dbgbase $_dbgbase $_TARGETNAME3 configure -dbgbase $_dbgbase
$_TARGETNAME3 configure -event reset-assert "arc_common_reset $_TARGETNAME3" $_TARGETNAME3 configure -event reset-assert "arc_common_reset $_TARGETNAME3"
set _coreid [expr $_coreid + 1] set _coreid [expr {$_coreid + 1}]
set _dbgbase [expr 0x00000000 | ($_coreid << 13)] set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
arc_hs_init_regs arc_hs_init_regs
# Enable L2 cache support for core 3. # Enable L2 cache support for core 3.
@ -89,8 +89,8 @@ $_TARGETNAME4 configure -coreid $_coreid
$_TARGETNAME4 configure -dbgbase $_dbgbase $_TARGETNAME4 configure -dbgbase $_dbgbase
# Flush L2$. # Flush L2$.
$_TARGETNAME4 configure -event reset-assert "arc_hs_reset $_TARGETNAME4" $_TARGETNAME4 configure -event reset-assert "arc_hs_reset $_TARGETNAME4"
set _coreid [expr $_coreid + 1] set _coreid [expr {$_coreid + 1}]
set _dbgbase [expr 0x00000000 | ($_coreid << 13)] set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
arc_hs_init_regs arc_hs_init_regs
# Enable L2 cache support for core 4. # Enable L2 cache support for core 4.
@ -104,8 +104,8 @@ target create $_TARGETNAME1 arcv2 -chain-position $_TARGETNAME1
$_TARGETNAME1 configure -coreid $_coreid $_TARGETNAME1 configure -coreid $_coreid
$_TARGETNAME1 configure -dbgbase $_dbgbase $_TARGETNAME1 configure -dbgbase $_dbgbase
$_TARGETNAME1 configure -event reset-assert "arc_common_reset $_TARGETNAME1" $_TARGETNAME1 configure -event reset-assert "arc_common_reset $_TARGETNAME1"
set _coreid [expr $_coreid + 1] set _coreid [expr {$_coreid + 1}]
set _dbgbase [expr 0x00000000 | ($_coreid << 13)] set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
arc_hs_init_regs arc_hs_init_regs
# Enable L2 cache support for core 1. # Enable L2 cache support for core 1.