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soc: nxp: imx: add i.MX95 Cortex-M7 support

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The i.MX95 applications processor features advanced graphics and
video cores, powerful vision and machine learning acceleration,
efficient CPU performance, real-time processing, and advanced
security with the integrated EdgeLock® secure enclave to support
energy-efficient edge computing.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit is contained in:
Yangbo Lu 2024-07-04 16:58:25 +09:00 • committed by Alberto Escolar
commit 5b6f07d1a6
10 changed files with 188 additions and 0 deletions
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2
soc/nxp/imx/imx9/CMakeLists.txt
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@ -3,4 +3,6 @@
if(CONFIG_SOC_MIMX9352)
add_subdirectory(imx93)
elseif(CONFIG_SOC_MIMX9596)
add_subdirectory(imx95)
endif()

7
soc/nxp/imx/imx9/imx95/CMakeLists.txt Normal file
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@ -0,0 +1,7 @@
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)
if(${CONFIG_MCUX_CORE_SUFFIX} STREQUAL "_cm7")
add_subdirectory(m7)
endif()

16
soc/nxp/imx/imx9/imx95/Kconfig Normal file
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@ -0,0 +1,16 @@
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
config SOC_MIMX9596_M7
select ARM
select CPU_CORTEX_M7
select CPU_HAS_FPU
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ICACHE
select CPU_HAS_DCACHE
select CPU_HAS_ARM_MPU
select ARM_MPU
select HAS_MCUX
config MCUX_CORE_SUFFIX
default "_cm7" if SOC_MIMX9596_M7

8
soc/nxp/imx/imx9/imx95/Kconfig.defconfig Normal file
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@ -0,0 +1,8 @@
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_IMX9
rsource "Kconfig.defconfig.*"
endif # SOC_SERIES_IMX9

22
soc/nxp/imx/imx9/imx95/Kconfig.defconfig.mimx95.m7 Normal file
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@ -0,0 +1,22 @@
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_MIMX9596_M7
DT_CHOSEN_Z_FLASH := zephyr,flash
config FLASH_SIZE
default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
config FLASH_BASE_ADDRESS
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
config NUM_IRQS
int
default 230
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 800000000
endif # SOC_MIMX9596_M7

21
soc/nxp/imx/imx9/imx95/Kconfig.soc Normal file
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@ -0,0 +1,21 @@
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
config SOC_MIMX9596
bool
select SOC_SERIES_IMX9
config SOC_MIMX9596_M7
bool
select SOC_MIMX9596
help
NXP i.MX95 M7
config SOC
default "mimx9596" if SOC_MIMX9596
config SOC_PART_NUMBER_MIMX9596AVZXN
bool
config SOC_PART_NUMBER
default "MIMX9596AVZXN" if SOC_PART_NUMBER_MIMX9596AVZXN

5
soc/nxp/imx/imx9/imx95/m7/CMakeLists.txt Normal file
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@ -0,0 +1,5 @@
# Copyright 2024 NXP
zephyr_include_directories(.)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

12
soc/nxp/imx/imx9/imx95/m7/soc.h Normal file
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@ -0,0 +1,12 @@
/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_NXP_IMX_IMX95_M7_SOC_H_
#define _SOC_NXP_IMX_IMX95_M7_SOC_H_
#include <fsl_device_registers.h>
#endif /* _SOC_NXP_IMX_IMX95_M7_SOC_H_ */

92
soc/nxp/imx/imx9/imx95/pinctrl_soc.h Normal file
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@ -0,0 +1,92 @@
/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_ARM64_NXP_IMX95_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM64_NXP_IMX95_PINCTRL_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PIN_CONFIG_TYPE_MUX 192
#define PIN_CONFIG_TYPE_CONFIG 193
#define PIN_CONFIG_TYPE_DAISY_ID 194
#define PIN_CONFIG_TYPE_DAISY_CFG 195
#define IOMUXC_MUX_MODE(x) IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x)
#define IOMUXC_SION(x) IOMUXC_SW_MUX_CTL_PAD_SION(x)
#define IOMUXC_MUXREG (IOMUXC_BASE)
#define IOMUXC_CFGREG (IOMUXC_BASE + 0x204)
#define IOMUXC_DAISYREG (IOMUXC_BASE + 0x408)
#define IOMUXC_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT
#define IOMUXC_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_OD_SHIFT
#define IOMUXC_BIAS_PULL_DOWN_SHIFT IOMUXC_SW_PAD_CTL_PAD_PD_SHIFT
#define IOMUXC_BIAS_PULL_UP_SHIFT IOMUXC_SW_PAD_CTL_PAD_PU_SHIFT
#define IOMUXC_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_FSEL1_SHIFT
#define IOMUXC_DRIVE_STRENGTH_SHIFT IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT
#define IOMUXC_INPUT_ENABLE_SHIFT 23 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
#define IOMUXC_INPUT_ENABLE(x) ((x >> IOMUXC_INPUT_ENABLE_SHIFT) & 0x1)
#define Z_PINCTRL_IOMUXC_PINCFG_INIT(node_id) \
((DT_PROP(node_id, input_schmitt_enable) << IOMUXC_INPUT_SCHMITT_ENABLE_SHIFT) | \
(DT_PROP(node_id, drive_open_drain) << IOMUXC_DRIVE_OPEN_DRAIN_SHIFT) | \
(DT_PROP(node_id, bias_pull_down) << IOMUXC_BIAS_PULL_DOWN_SHIFT) | \
(DT_PROP(node_id, bias_pull_up) << IOMUXC_BIAS_PULL_UP_SHIFT) | \
(DT_ENUM_IDX(node_id, slew_rate) << IOMUXC_SLEW_RATE_SHIFT) | \
((~(0xff << DT_ENUM_IDX(node_id, drive_strength))) << IOMUXC_DRIVE_STRENGTH_SHIFT) | \
(DT_PROP(node_id, input_enable) << IOMUXC_INPUT_ENABLE_SHIFT))
/* This struct must be present. It is used by the mcux gpio driver */
struct pinctrl_soc_pinmux {
uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
uint8_t mux_mode: 4; /*!< Mux value for SW_PAD_MUX register */
uint32_t input_daisy: 4; /*!< Mux value for SELECT_INPUT_DAISY register */
};
struct pinctrl_soc_pin {
struct pinctrl_soc_pinmux pinmux;
uint32_t pin_ctrl_flags; /*!< value to write to IOMUXC_SW_PAD_CTL register */
};
typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
/* This definition must be present. It is used by the mcux gpio driver */
#define IOMUXC_PINMUX(node_id) \
{ \
.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \
.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \
.input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \
.mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \
.input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \
}
#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \
IOMUXC_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
{ \
.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
.pin_ctrl_flags = Z_PINCTRL_IOMUXC_PINCFG_INIT(group_id), \
},
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
Z_PINCTRL_STATE_PIN_INIT)};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_SOC_ARM64_NXP_IMX95_PINCTRL_SOC_H_ */

3
soc/nxp/imx/soc.yml
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@ -48,6 +48,9 @@ family:
cpuclusters:
- name: a55
- name: m33
- name: mimx9596
cpuclusters:
- name: m7
- name: imx6sx
socs:
- name: mcimx6x