drivers: i2s: introduce CAVS I2S
Implements the driver for Intel CAVS I2S. Only Playback is currently supported. Change-Id: I7b816f9736dc35e79a81d3664d6405dc0aac15b4 Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Rajavardhan Gundi
Anas Nashif
parent
cea1c75e2b
commit
5b6f02442b
7 changed files with 1049 additions and 0 deletions
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@ -160,3 +160,15 @@ void dcache_writeback_region(void *addr, size_t size)
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{
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xthal_dcache_region_writeback(addr, size);
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}
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void dcache_invalidate_region(void *addr, size_t size)
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{
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xthal_dcache_region_invalidate(addr, size);
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}
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void setup_ownership_i2s(void)
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{
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u32_t value = I2S_OWNSEL(0) | I2S_OWNSEL(1) |
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I2S_OWNSEL(2) | I2S_OWNSEL(3);
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*(volatile u32_t *)SUE_DSPIOPO_REG |= value;
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}
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@ -100,11 +100,30 @@
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#define DMA_HANDSHAKE_SSP3_TX 8
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#define DMA_HANDSHAKE_SSP3_RX 9
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/* I2S */
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#define I2S0_CAVS_IRQ 0x00000010
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#define I2S1_CAVS_IRQ 0x00000110
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#define I2S2_CAVS_IRQ 0x00000210
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#define I2S3_CAVS_IRQ 0x00000310
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#define SSP_SIZE 0x0000200
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#define SSP_BASE(x) (0x00077000 + (x) * SSP_SIZE)
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#define SOC_INTEL_S1000_MCK_XTAL_FREQ_HZ 38400000
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/* address of I2S ownership register. We need to properly configure
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* this register in order to access the I2S registers.
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*/
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#define SUE_DSP_RES_ALLOC_REG_BASE 0x00071A60
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#define SUE_DSPIOPO_REG (SUE_DSP_RES_ALLOC_REG_BASE + 0x08)
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#define I2S_OWNSEL(x) (0x1 << (8 + (x)))
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extern void _soc_irq_enable(u32_t irq);
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extern void _soc_irq_disable(u32_t irq);
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extern void setup_ownership_dma0(void);
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extern void setup_ownership_dma1(void);
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extern void setup_ownership_dma2(void);
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extern void dcache_writeback_region(void *addr, size_t size);
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extern void setup_ownership_i2s(void);
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#endif /* __INC_SOC_H */
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@ -1 +1,2 @@
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zephyr_sources_ifdef(CONFIG_I2S_SAM_SSC i2s_sam_ssc.c)
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zephyr_sources_ifdef(CONFIG_I2S_CAVS i2s_cavs.c)
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59
drivers/i2s/Kconfig.cavs
Normal file
59
drivers/i2s/Kconfig.cavs
Normal file
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@ -0,0 +1,59 @@
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# Kconfig - Intel S1000 I2S configuration options
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#
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# Copyright (c) 2017 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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menuconfig I2S_CAVS
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bool "Intel I2S (SSP) Bus Driver"
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depends on BOARD_INTEL_S1000_CRB
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select DMA
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default n
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help
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Enable Inter Sound (I2S) bus driver for Intel_S1000 based on
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Synchronous Serial Port (SSP) module.
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if I2S_CAVS
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config I2S_CAVS_TX_BLOCK_COUNT
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int "TX queue length"
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default 4
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help
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The maximum number of blocks that can be accommodated in the Tx queue.
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config I2S_CAVS_0_NAME
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string "I2S 0 device name"
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default "I2S_0"
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config I2S_CAVS_0_IRQ_PRI
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int "Interrupt priority"
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default 0
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config I2S_CAVS_DMA_NAME
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string "DMA device name"
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default "DMA_0"
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help
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Name of the DMA device this device driver can use.
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config I2S_CAVS_0_DMA_TX_CHANNEL
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int "DMA TX channel"
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default 2
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help
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DMA channel number to use for TX transfers.
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config I2S_CAVS_1_NAME
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string "I2S 1 device name"
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default "I2S_1"
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config I2S_CAVS_1_IRQ_PRI
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int "Interrupt priority"
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default 0
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config I2S_CAVS_1_DMA_TX_CHANNEL
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int "DMA TX channel"
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default 4
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help
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DMA channel number to use for TX transfers.
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endif # I2S_CAVS
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798
drivers/i2s/i2s_cavs.c
Normal file
798
drivers/i2s/i2s_cavs.c
Normal file
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@ -0,0 +1,798 @@
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/*
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* Copyright (c) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** @file
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* @brief I2S bus (SSP) driver for Intel CAVS.
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*
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* Limitations:
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* - DMA is used in simple single block transfer mode (with linked list
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* enabled) and "interrupt on full transfer completion" mode.
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*/
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#include <errno.h>
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#include <string.h>
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#include <misc/__assert.h>
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <dma.h>
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#include <i2s.h>
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#include <soc.h>
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#include "i2s_cavs.h"
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#define SYS_LOG_DOMAIN "dev/i2s_cavs"
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#define SYS_LOG_LEVEL CONFIG_SYS_LOG_I2S_LEVEL
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#include <logging/sys_log.h>
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#ifdef CONFIG_DCACHE_WRITEBACK
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#define DCACHE_INVALIDATE(addr, size) \
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{ dcache_invalidate_region(addr, size); }
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#define DCACHE_CLEAN(addr, size) \
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{ dcache_writeback_region(addr, size); }
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#else
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#define DCACHE_INVALIDATE(addr, size) \
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do { } while (0)
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#define DCACHE_CLEAN(addr, size) \
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do { } while (0)
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#endif
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#define CAVS_SSP_WORD_SIZE_BITS_MIN 2
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#define CAVS_SSP_WORD_SIZE_BITS_MAX 32
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#define CAVS_SSP_WORD_PER_FRAME_MIN 1
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#define CAVS_SSP_WORD_PER_FRAME_MAX 16
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struct queue_item {
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void *mem_block;
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size_t size;
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};
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/* Minimal ring buffer implementation:
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* buf - holds the pointer to Queue items
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* len - Max number of Queue items that can be referenced
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* head - current write index number
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* tail - current read index number
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*/
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struct ring_buf {
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struct queue_item *buf;
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u16_t len;
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u16_t head;
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u16_t tail;
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};
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/* This indicates the Tx/Rx stream. Most members of the stream are
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* self-explanatory except for sem.
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* sem - This is initialized to CONFIG_I2S_CAVS_TX_BLOCK_COUNT. If at all
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* mem_block_queue gets filled with the MAX blocks configured, this semaphore
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* ensures nothing gets written into the mem_block_queue before a slot gets
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* freed (which happens when a block gets read out).
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*/
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struct stream {
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s32_t state;
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struct k_sem sem;
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u32_t dma_channel;
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struct dma_config dma_cfg;
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struct i2s_config cfg;
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struct ring_buf mem_block_queue;
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void *mem_block;
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bool last_block;
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int (*stream_start)(struct stream *, struct i2s_cavs_ssp *const,
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struct device *);
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void (*stream_disable)(struct stream *, struct i2s_cavs_ssp *const,
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struct device *);
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void (*queue_drop)(struct stream *);
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};
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struct i2s_cavs_config {
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struct i2s_cavs_ssp *regs;
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u32_t irq_id;
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void (*irq_config)(void);
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};
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/* Device run time data */
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struct i2s_cavs_dev_data {
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struct device *dev_dma;
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struct stream tx;
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};
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#define DEV_NAME(dev) ((dev)->config->name)
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#define DEV_CFG(dev) \
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((const struct i2s_cavs_config *const)(dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct i2s_cavs_dev_data *const)(dev)->driver_data)
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static struct device *get_dev_from_dma_channel(u32_t dma_channel);
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static void dma_tx_callback(struct device *, u32_t, int);
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static void tx_stream_disable(struct stream *, struct i2s_cavs_ssp *const,
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struct device *);
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static inline u16_t modulo_inc(u16_t val, u16_t max)
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{
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val++;
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return (val < max) ? val : 0;
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}
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/*
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* Get data from the queue
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*/
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static int queue_get(struct ring_buf *rb, u8_t mode, void **mem_block,
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size_t *size)
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{
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unsigned int key;
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key = irq_lock();
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/* In case of ping-pong mode, the buffers are not freed after
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* reading. They are fixed in size. Another thread will populate
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* the pong buffer while the ping buffer is being read out and
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* vice versa. Hence, we just need to keep reading from buffer0
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* (ping buffer) followed by buffer1 (pong buffer) and the same
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* cycle continues.
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*
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* In case of non-ping-pong modes, each buffer is freed after it
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* is read. The tail pointer will keep progressing depending upon
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* the reads. The head pointer will move whenever there's a write.
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* If tail equals head, it would mean we have read everything there
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* is and the buffer is empty.
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*/
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if (rb->tail == rb->head) {
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if ((mode & I2S_OPT_PINGPONG) == I2S_OPT_PINGPONG) {
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/* Point back to the first element */
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rb->tail = 0;
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} else {
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/* Ring buffer is empty */
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irq_unlock(key);
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return -ENOMEM;
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}
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}
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*mem_block = rb->buf[rb->tail].mem_block;
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*size = rb->buf[rb->tail].size;
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rb->tail = modulo_inc(rb->tail, rb->len);
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irq_unlock(key);
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return 0;
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}
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/*
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* Put data in the queue
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*/
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static int queue_put(struct ring_buf *rb, u8_t mode, void *mem_block,
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size_t size)
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{
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u16_t head_next;
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unsigned int key;
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key = irq_lock();
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head_next = rb->head;
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head_next = modulo_inc(head_next, rb->len);
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/* In case of ping-pong mode, the below comparison incorrectly
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* leads to complications as the buffers are always predefined.
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* Hence excluding ping-pong mode from this comparison.
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*/
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if ((mode & I2S_OPT_PINGPONG) != I2S_OPT_PINGPONG) {
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if (head_next == rb->tail) {
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/* Ring buffer is full */
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irq_unlock(key);
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return -ENOMEM;
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}
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}
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rb->buf[rb->head].mem_block = mem_block;
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rb->buf[rb->head].size = size;
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rb->head = head_next;
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irq_unlock(key);
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return 0;
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}
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static int start_dma(struct device *dev_dma, u32_t channel,
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struct dma_config *cfg, void *src, void *dst,
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u32_t blk_size)
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{
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int ret;
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struct dma_block_config blk_cfg = {
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.block_size = blk_size,
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.source_address = (u32_t)src,
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.dest_address = (u32_t)dst,
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};
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cfg->head_block = &blk_cfg;
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ret = dma_config(dev_dma, channel, cfg);
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if (ret < 0) {
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SYS_LOG_ERR("dma_config failed: %d", ret);
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return ret;
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}
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ret = dma_start(dev_dma, channel);
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if (ret < 0) {
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SYS_LOG_ERR("dma_start failed: %d", ret);
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}
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return ret;
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}
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/* This function is executed in the interrupt context */
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static void dma_tx_callback(struct device *dev_dma, u32_t channel, int status)
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{
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struct device *dev = get_dev_from_dma_channel(channel);
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const struct i2s_cavs_config *const dev_cfg = DEV_CFG(dev);
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struct i2s_cavs_dev_data *const dev_data = DEV_DATA(dev);
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struct i2s_cavs_ssp *const ssp = dev_cfg->regs;
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struct stream *strm = &dev_data->tx;
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size_t mem_block_size;
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int ret;
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__ASSERT_NO_MSG(strm->mem_block != NULL);
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if ((strm->cfg.options & I2S_OPT_PINGPONG) != I2S_OPT_PINGPONG) {
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/* All block data sent */
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k_mem_slab_free(strm->cfg.mem_slab, &strm->mem_block);
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strm->mem_block = NULL;
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}
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/* Stop transmission if there was an error */
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if (strm->state == I2S_STATE_ERROR) {
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SYS_LOG_DBG("TX error detected");
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goto tx_disable;
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}
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/* Stop transmission if we were requested */
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if (strm->last_block) {
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strm->state = I2S_STATE_READY;
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goto tx_disable;
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}
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/* Prepare to send the next data block */
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ret = queue_get(&strm->mem_block_queue, strm->cfg.options,
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&strm->mem_block, &mem_block_size);
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if (ret < 0) {
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if (strm->state == I2S_STATE_STOPPING) {
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strm->state = I2S_STATE_READY;
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} else {
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strm->state = I2S_STATE_ERROR;
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}
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goto tx_disable;
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}
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k_sem_give(&strm->sem);
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/* Assure cache coherency before DMA read operation */
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DCACHE_CLEAN(strm->mem_block, mem_block_size);
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ret = start_dma(dev_data->dev_dma, strm->dma_channel, &strm->dma_cfg,
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strm->mem_block, (void *)&(ssp->ssd),
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mem_block_size);
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if (ret < 0) {
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SYS_LOG_DBG("Failed to start TX DMA transfer: %d", ret);
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goto tx_disable;
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}
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return;
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tx_disable:
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tx_stream_disable(strm, ssp, dev_data->dev_dma);
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}
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static int i2s_cavs_configure(struct device *dev, enum i2s_dir dir,
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struct i2s_config *i2s_cfg)
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{
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const struct i2s_cavs_config *const dev_cfg = DEV_CFG(dev);
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struct i2s_cavs_dev_data *const dev_data = DEV_DATA(dev);
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struct i2s_cavs_ssp *const ssp = dev_cfg->regs;
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u8_t num_words = i2s_cfg->channels;
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u8_t word_size_bits = i2s_cfg->word_size;
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u8_t word_size_bytes;
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u32_t bit_clk_freq, mclk;
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struct stream *strm;
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u32_t ssc0;
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u32_t ssc1;
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u32_t ssc2;
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u32_t ssc3;
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u32_t sspsp;
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u32_t sspsp2;
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u32_t sstsa;
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u32_t ssrsa;
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u32_t ssto;
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u32_t ssioc;
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u32_t mdiv;
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u32_t i2s_m;
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u32_t i2s_n;
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u32_t frame_len = 0;
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bool inverted_frame = false;
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if (dir == I2S_DIR_TX) {
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strm = &dev_data->tx;
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} else {
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SYS_LOG_ERR("TX direction must be selected");
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return -EINVAL;
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}
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if (strm->state != I2S_STATE_NOT_READY &&
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strm->state != I2S_STATE_READY) {
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SYS_LOG_ERR("invalid state");
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return -EINVAL;
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}
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if (i2s_cfg->frame_clk_freq == 0) {
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strm->queue_drop(strm);
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memset(&strm->cfg, 0, sizeof(struct i2s_config));
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strm->state = I2S_STATE_NOT_READY;
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return 0;
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}
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if (word_size_bits < CAVS_SSP_WORD_SIZE_BITS_MIN ||
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word_size_bits > CAVS_SSP_WORD_SIZE_BITS_MAX) {
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SYS_LOG_ERR("Unsupported I2S word size");
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return -EINVAL;
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}
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if (num_words < CAVS_SSP_WORD_PER_FRAME_MIN ||
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num_words > CAVS_SSP_WORD_PER_FRAME_MAX) {
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SYS_LOG_ERR("Unsupported words per frame number");
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return -EINVAL;
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}
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memcpy(&strm->cfg, i2s_cfg, sizeof(struct i2s_config));
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/* reset SSP settings */
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/* sscr0 dynamic settings are DSS, EDSS, SCR, FRDC, ECS */
|
||||
/*
|
||||
* FIXME: MOD, ACS, NCS are not set,
|
||||
* no support for network mode for now
|
||||
*/
|
||||
ssc0 = SSCR0_PSP | SSCR0_RIM | SSCR0_TIM;
|
||||
|
||||
/* sscr1 dynamic settings are SFRMDIR, SCLKDIR, SCFR */
|
||||
ssc1 = SSCR1_TTE | SSCR1_TTELP | SSCR1_RWOT | SSCR1_TRAIL;
|
||||
|
||||
/* sscr2 dynamic setting is LJDFD */
|
||||
ssc2 = SSCR2_SDFD | SSCR2_TURM1;
|
||||
|
||||
/* sscr3 dynamic settings are TFT, RFT */
|
||||
ssc3 = 0;
|
||||
|
||||
/* sspsp dynamic settings are SCMODE, SFRMP, DMYSTRT, SFRMWDTH */
|
||||
sspsp = 0;
|
||||
|
||||
/* sspsp2 no dynamic setting */
|
||||
sspsp2 = 0x0;
|
||||
|
||||
/* ssioc dynamic setting is SFCR */
|
||||
ssioc = SSIOC_SCOE;
|
||||
|
||||
/* i2s_m M divider setting, default 1 */
|
||||
i2s_m = 0x1;
|
||||
|
||||
/* i2s_n N divider setting, default 1 */
|
||||
i2s_n = 0x1;
|
||||
|
||||
/* ssto no dynamic setting */
|
||||
ssto = 0x0;
|
||||
|
||||
/* sstsa dynamic setting is TTSA, default 2 slots */
|
||||
/* TODO: Expand I2s.h to make this configurable */
|
||||
sstsa = (0x1 << 8) | (0x3 << 0);
|
||||
|
||||
/* ssrsa dynamic setting is RTSA, default 2 slots */
|
||||
/* TODO: Expand I2s.h to make this configurable */
|
||||
ssrsa = 0;
|
||||
|
||||
/* clock masters */
|
||||
ssc1 &= ~SSCR1_SFRMDIR;
|
||||
|
||||
/* codec is clk slave & FRM slave */
|
||||
/* TODO: Expand I2s.h to make this configurable */
|
||||
ssc1 |= SSCR1_SCFR;
|
||||
ssioc |= SSIOC_SFCR;
|
||||
|
||||
/* clock signal polarity */
|
||||
switch (i2s_cfg->format & I2S_FMT_CLK_FORMAT_MASK) {
|
||||
case I2S_FMT_CLK_NF_NB:
|
||||
break;
|
||||
|
||||
case I2S_FMT_CLK_NF_IB:
|
||||
sspsp |= SSPSP_SCMODE(2);
|
||||
inverted_frame = true; /* handled later with format */
|
||||
break;
|
||||
|
||||
case I2S_FMT_CLK_IF_NB:
|
||||
break;
|
||||
|
||||
case I2S_FMT_CLK_IF_IB:
|
||||
sspsp |= SSPSP_SCMODE(2);
|
||||
inverted_frame = true; /* handled later with format */
|
||||
break;
|
||||
|
||||
default:
|
||||
SYS_LOG_ERR("Unsupported Clock format");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ssc0 |= SSCR0_MOD | SSCR0_ACS;
|
||||
|
||||
mclk = SOC_INTEL_S1000_MCK_XTAL_FREQ_HZ;
|
||||
bit_clk_freq = i2s_cfg->frame_clk_freq * word_size_bits * num_words;
|
||||
|
||||
/* BCLK is generated from MCLK - must be divisible */
|
||||
if (mclk % bit_clk_freq) {
|
||||
SYS_LOG_ERR("MCLK is not a factor of BCLK");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* divisor must be within SCR range */
|
||||
mdiv = (mclk / bit_clk_freq) - 1;
|
||||
if (mdiv > (SSCR0_SCR_MASK >> 8)) {
|
||||
SYS_LOG_ERR("Divisor is not within SCR range");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* set the SCR divisor */
|
||||
ssc0 |= SSCR0_SCR(mdiv);
|
||||
|
||||
/* word_size_bits must be <= 38 for SSP */
|
||||
if (word_size_bits > 38) {
|
||||
SYS_LOG_ERR("word size bits is more than 38");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* format */
|
||||
switch (i2s_cfg->format & I2S_FMT_DATA_FORMAT_MASK) {
|
||||
|
||||
case I2S_FMT_DATA_FORMAT_I2S:
|
||||
ssc0 |= SSCR0_FRDC(i2s_cfg->channels);
|
||||
|
||||
/* set asserted frame length */
|
||||
frame_len = word_size_bits;
|
||||
|
||||
/* handle frame polarity, I2S default is falling/active low */
|
||||
sspsp |= SSPSP_SFRMP(!inverted_frame);
|
||||
break;
|
||||
|
||||
case I2S_FMT_DATA_FORMAT_LEFT_JUSTIFIED:
|
||||
ssc0 |= SSCR0_FRDC(i2s_cfg->channels);
|
||||
|
||||
/* LJDFD enable */
|
||||
ssc2 &= ~SSCR2_LJDFD;
|
||||
|
||||
/* set asserted frame length */
|
||||
frame_len = word_size_bits;
|
||||
|
||||
/* LEFT_J default is rising/active high, opposite of I2S */
|
||||
sspsp |= SSPSP_SFRMP(inverted_frame);
|
||||
break;
|
||||
|
||||
case I2S_FMT_DATA_FORMAT_PCM_SHORT:
|
||||
case I2S_FMT_DATA_FORMAT_PCM_LONG:
|
||||
default:
|
||||
SYS_LOG_ERR("Unsupported I2S data format");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
sspsp |= SSPSP_SFRMWDTH(frame_len);
|
||||
|
||||
if (word_size_bits > 16) {
|
||||
ssc0 |= (SSCR0_EDSS | SSCR0_DSIZE(word_size_bits - 16));
|
||||
} else {
|
||||
ssc0 |= SSCR0_DSIZE(word_size_bits);
|
||||
}
|
||||
|
||||
ssp->ssc0 = ssc0;
|
||||
ssp->ssc1 = ssc1;
|
||||
ssp->ssc2 = ssc2;
|
||||
ssp->ssc3 = ssc3;
|
||||
ssp->sspsp2 = sspsp2;
|
||||
ssp->sspsp = sspsp;
|
||||
ssp->ssioc = ssioc;
|
||||
ssp->ssto = ssto;
|
||||
ssp->sstsa = sstsa;
|
||||
ssp->ssrsa = ssrsa;
|
||||
|
||||
/* Set up DMA channel parameters */
|
||||
word_size_bytes = (word_size_bits + 7) / 8;
|
||||
strm->dma_cfg.source_data_size = word_size_bytes;
|
||||
strm->dma_cfg.dest_data_size = word_size_bytes;
|
||||
|
||||
strm->state = I2S_STATE_READY;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tx_stream_start(struct stream *strm,
|
||||
struct i2s_cavs_ssp *const ssp,
|
||||
struct device *dev_dma)
|
||||
{
|
||||
size_t mem_block_size;
|
||||
int ret;
|
||||
|
||||
ret = queue_get(&strm->mem_block_queue, strm->cfg.options,
|
||||
&strm->mem_block, &mem_block_size);
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
k_sem_give(&strm->sem);
|
||||
|
||||
/* Assure cache coherency before DMA read operation */
|
||||
DCACHE_CLEAN(strm->mem_block, mem_block_size);
|
||||
|
||||
ret = start_dma(dev_dma, strm->dma_channel, &strm->dma_cfg,
|
||||
strm->mem_block, (void *)&(ssp->ssd),
|
||||
mem_block_size);
|
||||
if (ret < 0) {
|
||||
SYS_LOG_ERR("Failed to start TX DMA transfer: %d", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* enable port */
|
||||
ssp->ssc0 |= SSCR0_SSE;
|
||||
|
||||
/* Enable DMA service request handshake logic. Though DMA is
|
||||
* already started, it won't work without the handshake logic.
|
||||
*/
|
||||
ssp->ssc1 |= SSCR1_TSRE;
|
||||
ssp->sstsa |= (0x1 << 8);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tx_stream_disable(struct stream *strm,
|
||||
struct i2s_cavs_ssp *const ssp,
|
||||
struct device *dev_dma)
|
||||
{
|
||||
/* Disable DMA service request handshake logic. Handshake is
|
||||
* not required now since DMA is not in operation.
|
||||
*/
|
||||
ssp->ssc1 &= ~SSCR1_TSRE;
|
||||
ssp->sstsa &= ~(0x1 << 8);
|
||||
|
||||
dma_stop(dev_dma, strm->dma_channel);
|
||||
|
||||
if (((strm->cfg.options & I2S_OPT_PINGPONG) != I2S_OPT_PINGPONG) &&
|
||||
(strm->mem_block != NULL)) {
|
||||
k_mem_slab_free(strm->cfg.mem_slab, &strm->mem_block);
|
||||
strm->mem_block = NULL;
|
||||
}
|
||||
strm->mem_block_queue.head = 0;
|
||||
strm->mem_block_queue.tail = 0;
|
||||
}
|
||||
|
||||
static void tx_queue_drop(struct stream *strm)
|
||||
{
|
||||
size_t size;
|
||||
void *mem_block;
|
||||
unsigned int n = 0;
|
||||
|
||||
while (queue_get(&strm->mem_block_queue, strm->cfg.options,
|
||||
&mem_block, &size) == 0) {
|
||||
if ((strm->cfg.options & I2S_OPT_PINGPONG)
|
||||
!= I2S_OPT_PINGPONG) {
|
||||
k_mem_slab_free(strm->cfg.mem_slab, &mem_block);
|
||||
n++;
|
||||
}
|
||||
}
|
||||
|
||||
strm->mem_block_queue.head = 0;
|
||||
strm->mem_block_queue.tail = 0;
|
||||
|
||||
for (; n > 0; n--) {
|
||||
k_sem_give(&strm->sem);
|
||||
}
|
||||
}
|
||||
|
||||
static int i2s_cavs_trigger(struct device *dev, enum i2s_dir dir,
|
||||
enum i2s_trigger_cmd cmd)
|
||||
{
|
||||
const struct i2s_cavs_config *const dev_cfg = DEV_CFG(dev);
|
||||
struct i2s_cavs_dev_data *const dev_data = DEV_DATA(dev);
|
||||
struct i2s_cavs_ssp *const ssp = dev_cfg->regs;
|
||||
struct stream *strm;
|
||||
unsigned int key;
|
||||
int ret;
|
||||
|
||||
if (dir == I2S_DIR_TX) {
|
||||
strm = &dev_data->tx;
|
||||
} else {
|
||||
SYS_LOG_ERR("TX direction must be selected");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (cmd) {
|
||||
case I2S_TRIGGER_START:
|
||||
if (strm->state != I2S_STATE_READY) {
|
||||
SYS_LOG_DBG("START trigger: invalid state");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
__ASSERT_NO_MSG(strm->mem_block == NULL);
|
||||
|
||||
ret = strm->stream_start(strm, ssp, dev_data->dev_dma);
|
||||
if (ret < 0) {
|
||||
SYS_LOG_DBG("START trigger failed %d", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
strm->state = I2S_STATE_RUNNING;
|
||||
strm->last_block = false;
|
||||
break;
|
||||
|
||||
case I2S_TRIGGER_STOP:
|
||||
key = irq_lock();
|
||||
if (strm->state != I2S_STATE_RUNNING) {
|
||||
irq_unlock(key);
|
||||
SYS_LOG_DBG("STOP trigger: invalid state");
|
||||
return -EIO;
|
||||
}
|
||||
strm->state = I2S_STATE_STOPPING;
|
||||
irq_unlock(key);
|
||||
strm->last_block = true;
|
||||
break;
|
||||
|
||||
case I2S_TRIGGER_DRAIN:
|
||||
key = irq_lock();
|
||||
if (strm->state != I2S_STATE_RUNNING) {
|
||||
irq_unlock(key);
|
||||
SYS_LOG_DBG("DRAIN trigger: invalid state");
|
||||
return -EIO;
|
||||
}
|
||||
strm->state = I2S_STATE_STOPPING;
|
||||
irq_unlock(key);
|
||||
break;
|
||||
|
||||
case I2S_TRIGGER_DROP:
|
||||
if (strm->state == I2S_STATE_NOT_READY) {
|
||||
SYS_LOG_DBG("DROP trigger: invalid state");
|
||||
return -EIO;
|
||||
}
|
||||
strm->stream_disable(strm, ssp, dev_data->dev_dma);
|
||||
strm->queue_drop(strm);
|
||||
strm->state = I2S_STATE_READY;
|
||||
break;
|
||||
|
||||
case I2S_TRIGGER_PREPARE:
|
||||
if (strm->state != I2S_STATE_ERROR) {
|
||||
SYS_LOG_DBG("PREPARE trigger: invalid state");
|
||||
return -EIO;
|
||||
}
|
||||
strm->state = I2S_STATE_READY;
|
||||
strm->queue_drop(strm);
|
||||
break;
|
||||
|
||||
default:
|
||||
SYS_LOG_ERR("Unsupported trigger command");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int i2s_cavs_write(struct device *dev, void *mem_block, size_t size)
|
||||
{
|
||||
struct i2s_cavs_dev_data *const dev_data = DEV_DATA(dev);
|
||||
struct stream *strm = &dev_data->tx;
|
||||
int ret;
|
||||
|
||||
if (dev_data->tx.state != I2S_STATE_RUNNING &&
|
||||
dev_data->tx.state != I2S_STATE_READY) {
|
||||
SYS_LOG_DBG("invalid state");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
ret = k_sem_take(&dev_data->tx.sem, dev_data->tx.cfg.timeout);
|
||||
if (ret < 0) {
|
||||
SYS_LOG_ERR("Failure taking sem");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Add data to the end of the TX queue */
|
||||
queue_put(&dev_data->tx.mem_block_queue, strm->cfg.options,
|
||||
mem_block, size);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* clear IRQ sources atm */
|
||||
static void i2s_cavs_isr(void *arg)
|
||||
{
|
||||
struct device *dev = (struct device *)arg;
|
||||
const struct i2s_cavs_config *const dev_cfg = DEV_CFG(dev);
|
||||
struct i2s_cavs_ssp *const ssp = dev_cfg->regs;
|
||||
u32_t temp;
|
||||
|
||||
/* clear IRQ */
|
||||
temp = ssp->sss;
|
||||
ssp->sss = temp;
|
||||
}
|
||||
|
||||
static int i2s1_cavs_initialize(struct device *dev)
|
||||
{
|
||||
const struct i2s_cavs_config *const dev_cfg = DEV_CFG(dev);
|
||||
struct i2s_cavs_dev_data *const dev_data = DEV_DATA(dev);
|
||||
|
||||
#ifdef CONFIG_SOC_INTEL_S1000
|
||||
setup_ownership_i2s();
|
||||
#endif
|
||||
|
||||
/* Configure interrupts */
|
||||
dev_cfg->irq_config();
|
||||
|
||||
/* Initialize semaphores */
|
||||
k_sem_init(&dev_data->tx.sem, CONFIG_I2S_CAVS_TX_BLOCK_COUNT,
|
||||
CONFIG_I2S_CAVS_TX_BLOCK_COUNT);
|
||||
|
||||
dev_data->dev_dma = device_get_binding(CONFIG_I2S_CAVS_DMA_NAME);
|
||||
if (!dev_data->dev_dma) {
|
||||
SYS_LOG_ERR("%s device not found", CONFIG_I2S_CAVS_DMA_NAME);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Enable module's IRQ */
|
||||
irq_enable(dev_cfg->irq_id);
|
||||
|
||||
SYS_LOG_INF("Device %s initialized", DEV_NAME(dev));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct i2s_driver_api i2s_cavs_driver_api = {
|
||||
.configure = i2s_cavs_configure,
|
||||
.write = i2s_cavs_write,
|
||||
.trigger = i2s_cavs_trigger,
|
||||
};
|
||||
|
||||
/* I2S1 */
|
||||
|
||||
static struct device DEVICE_NAME_GET(i2s1_cavs);
|
||||
|
||||
static struct device *get_dev_from_dma_channel(u32_t dma_channel)
|
||||
{
|
||||
return &DEVICE_NAME_GET(i2s1_cavs);
|
||||
}
|
||||
|
||||
struct queue_item tx_0_ring_buf[CONFIG_I2S_CAVS_TX_BLOCK_COUNT + 1];
|
||||
|
||||
static void i2s1_irq_config(void)
|
||||
{
|
||||
IRQ_CONNECT(I2S1_CAVS_IRQ, CONFIG_I2S_1_IRQ_PRI, i2s_cavs_isr,
|
||||
DEVICE_GET(i2s1_cavs), 0);
|
||||
}
|
||||
|
||||
static const struct i2s_cavs_config i2s1_cavs_config = {
|
||||
.regs = (struct i2s_cavs_ssp *)SSP_BASE(1),
|
||||
.irq_id = I2S1_CAVS_IRQ,
|
||||
.irq_config = i2s1_irq_config,
|
||||
};
|
||||
|
||||
static struct i2s_cavs_dev_data i2s1_cavs_data = {
|
||||
.tx = {
|
||||
.dma_channel = CONFIG_I2S_CAVS_1_DMA_TX_CHANNEL,
|
||||
.dma_cfg = {
|
||||
.source_data_size = 1,
|
||||
.dest_data_size = 1,
|
||||
.source_burst_length = 1,
|
||||
.dest_burst_length = 1,
|
||||
.dma_callback = dma_tx_callback,
|
||||
.complete_callback_en = 0,
|
||||
.error_callback_en = 1,
|
||||
.block_count = 1,
|
||||
.channel_direction = MEMORY_TO_PERIPHERAL,
|
||||
.dma_slot = DMA_HANDSHAKE_SSP1_TX,
|
||||
},
|
||||
.mem_block_queue.buf = tx_0_ring_buf,
|
||||
.mem_block_queue.len = ARRAY_SIZE(tx_0_ring_buf),
|
||||
.stream_start = tx_stream_start,
|
||||
.stream_disable = tx_stream_disable,
|
||||
.queue_drop = tx_queue_drop,
|
||||
},
|
||||
};
|
||||
|
||||
DEVICE_AND_API_INIT(i2s1_cavs, CONFIG_I2S_CAVS_1_NAME, &i2s1_cavs_initialize,
|
||||
&i2s1_cavs_data, &i2s1_cavs_config, POST_KERNEL,
|
||||
CONFIG_I2S_INIT_PRIORITY, &i2s_cavs_driver_api);
|
||||
137
drivers/i2s/i2s_cavs.h
Normal file
137
drivers/i2s/i2s_cavs.h
Normal file
|
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief I2S bus (SSP) driver for Intel CAVS.
|
||||
*
|
||||
* Limitations:
|
||||
* - DMA is used in simple single block transfer mode (with linked list
|
||||
* enabled) and "interrupt on full transfer completion" mode.
|
||||
*/
|
||||
|
||||
#ifndef _I2S_CAVS_H_
|
||||
#define _I2S_CAVS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct i2s_cavs_ssp {
|
||||
u32_t ssc0; /* 0x00 - Control0 */
|
||||
u32_t ssc1; /* 0x04 - Control1 */
|
||||
u32_t sss; /* 0x08 - Status */
|
||||
u32_t ssit; /* 0x0C - Interrupt Test */
|
||||
u32_t ssd; /* 0x10 - Data */
|
||||
u32_t reserved0[5];
|
||||
u32_t ssto; /* 0x28 - Time Out */
|
||||
u32_t sspsp; /* 0x2C - Programmable Serial Protocol */
|
||||
u32_t sstsa; /* 0x30 - TX Time Slot Active */
|
||||
u32_t ssrsa; /* 0x34 - RX Time Slot Active */
|
||||
u32_t sstss; /* 0x38 - Time Slot Status */
|
||||
u32_t reserved1;
|
||||
u32_t ssc2; /* 0x40 - Command / Status 2 */
|
||||
u32_t sspsp2; /* 0x44 - Programmable Serial Protocol 2 */
|
||||
u32_t ssc3; /* 0x48 - Command / Status 3 */
|
||||
u32_t ssioc; /* 0x4C - IO Control */
|
||||
};
|
||||
|
||||
/* SSCR0 bits */
|
||||
#define SSCR0_DSS_MASK (0x0000000f)
|
||||
#define SSCR0_DSIZE(x) ((x) - 1)
|
||||
#define SSCR0_FRF (0x00000030)
|
||||
#define SSCR0_MOT (00 << 4)
|
||||
#define SSCR0_TI (1 << 4)
|
||||
#define SSCR0_NAT (2 << 4)
|
||||
#define SSCR0_PSP (3 << 4)
|
||||
#define SSCR0_ECS (1 << 6)
|
||||
#define SSCR0_SSE (1 << 7)
|
||||
#define SSCR0_SCR_MASK (0x000fff00)
|
||||
#define SSCR0_SCR(x) ((x) << 8)
|
||||
#define SSCR0_EDSS (1 << 20)
|
||||
#define SSCR0_NCS (1 << 21)
|
||||
#define SSCR0_RIM (1 << 22)
|
||||
#define SSCR0_TIM (1 << 23)
|
||||
#define SSCR0_FRDC(x) (((x) - 1) << 24)
|
||||
#define SSCR0_ACS (1 << 30)
|
||||
#define SSCR0_MOD (1 << 31)
|
||||
|
||||
/* SSCR1 bits */
|
||||
#define SSCR1_RIE (1 << 0)
|
||||
#define SSCR1_TIE (1 << 1)
|
||||
#define SSCR1_LBM (1 << 2)
|
||||
#define SSCR1_SPO (1 << 3)
|
||||
#define SSCR1_SPH (1 << 4)
|
||||
#define SSCR1_MWDS (1 << 5)
|
||||
#define SSCR1_EFWR (1 << 14)
|
||||
#define SSCR1_STRF (1 << 15)
|
||||
#define SSCR1_IFS (1 << 16)
|
||||
#define SSCR1_PINTE (1 << 18)
|
||||
#define SSCR1_TINTE (1 << 19)
|
||||
#define SSCR1_RSRE (1 << 20)
|
||||
#define SSCR1_TSRE (1 << 21)
|
||||
#define SSCR1_TRAIL (1 << 22)
|
||||
#define SSCR1_RWOT (1 << 23)
|
||||
#define SSCR1_SFRMDIR (1 << 24)
|
||||
#define SSCR1_SCLKDIR (1 << 25)
|
||||
#define SSCR1_ECRB (1 << 26)
|
||||
#define SSCR1_ECRA (1 << 27)
|
||||
#define SSCR1_SCFR (1 << 28)
|
||||
#define SSCR1_EBCEI (1 << 29)
|
||||
#define SSCR1_TTE (1 << 30)
|
||||
#define SSCR1_TTELP (1 << 31)
|
||||
|
||||
/* SSCR2 bits */
|
||||
#define SSCR2_TURM1 (1 << 1)
|
||||
#define SSCR2_SDFD (1 << 14)
|
||||
#define SSCR2_SDPM (1 << 16)
|
||||
#define SSCR2_LJDFD (1 << 17)
|
||||
|
||||
/* SSR bits */
|
||||
#define SSSR_TNF (1 << 2)
|
||||
#define SSSR_RNE (1 << 3)
|
||||
#define SSSR_BSY (1 << 4)
|
||||
#define SSSR_TFS (1 << 5)
|
||||
#define SSSR_RFS (1 << 6)
|
||||
#define SSSR_ROR (1 << 7)
|
||||
|
||||
/* SSPSP bits */
|
||||
#define SSPSP_SCMODE(x) ((x) << 0)
|
||||
#define SSPSP_SFRMP(x) ((x) << 2)
|
||||
#define SSPSP_ETDS (1 << 3)
|
||||
#define SSPSP_STRTDLY(x) ((x) << 4)
|
||||
#define SSPSP_DMYSTRT(x) ((x) << 7)
|
||||
#define SSPSP_SFRMDLY(x) ((x) << 9)
|
||||
#define SSPSP_SFRMWDTH(x) ((x) << 16)
|
||||
#define SSPSP_DMYSTOP(x) ((x) << 23)
|
||||
#define SSPSP_FSRT (1 << 25)
|
||||
#define SSPSP_EDMYSTOP(x) ((x) << 26)
|
||||
|
||||
/* SSTSA bits */
|
||||
#define SSTSA_TTSA(x) (1 << x)
|
||||
#define SSTSA_TXEN (1 << 8)
|
||||
|
||||
/* SSRSA bits */
|
||||
#define SSRSA_RTSA(x) (1 << x)
|
||||
#define SSRSA_RXEN (1 << 8)
|
||||
|
||||
/* SSCR3 bits */
|
||||
#define SSCR3_TFL_MASK (0x0000003f)
|
||||
#define SSCR3_RFL_MASK (0x00003f00)
|
||||
#define SSCR3_TFT_MASK (0x003f0000)
|
||||
#define SSCR3_TX(x) (((x) - 1) << 16)
|
||||
#define SSCR3_RFT_MASK (0x3f000000)
|
||||
#define SSCR3_RX(x) (((x) - 1) << 24)
|
||||
|
||||
/* SSIOC bits */
|
||||
#define SSIOC_TXDPDEB (1 << 1)
|
||||
#define SSIOC_SFCR (1 << 4)
|
||||
#define SSIOC_SCOE (1 << 5)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _I2S_CAVS_H_ */
|
||||
|
|
@ -148,11 +148,24 @@ typedef u8_t i2s_fmt_t;
|
|||
#define I2S_FMT_DATA_ORDER_LSB (1 << 3)
|
||||
/** Invert bit ordering, send LSB first */
|
||||
#define I2S_FMT_DATA_ORDER_INV I2S_FMT_DATA_ORDER_LSB
|
||||
|
||||
/** Data Format bit field position. */
|
||||
#define I2S_FMT_CLK_FORMAT_SHIFT 4
|
||||
/** Data Format bit field mask. */
|
||||
#define I2S_FMT_CLK_FORMAT_MASK (0x3 << I2S_FMT_CLK_FORMAT_SHIFT)
|
||||
|
||||
/** Invert bit clock */
|
||||
#define I2S_FMT_BIT_CLK_INV (1 << 4)
|
||||
/** Invert frame clock */
|
||||
#define I2S_FMT_FRAME_CLK_INV (1 << 5)
|
||||
|
||||
/** NF represents "Normal Frame" whereas IF represents "Inverted Frame"
|
||||
* NB represents "Normal Bit Clk" whereas IB represents "Inverted Bit clk"
|
||||
*/
|
||||
#define I2S_FMT_CLK_NF_NB (0 << I2S_FMT_CLK_FORMAT_SHIFT)
|
||||
#define I2S_FMT_CLK_NF_IB (1 << I2S_FMT_CLK_FORMAT_SHIFT)
|
||||
#define I2S_FMT_CLK_IF_NB (2 << I2S_FMT_CLK_FORMAT_SHIFT)
|
||||
#define I2S_FMT_CLK_IF_IB (3 << I2S_FMT_CLK_FORMAT_SHIFT)
|
||||
|
||||
typedef u8_t i2s_opt_t;
|
||||
|
||||
|
|
@ -168,6 +181,7 @@ typedef u8_t i2s_opt_t;
|
|||
#define I2S_OPT_FRAME_CLK_MASTER (0 << 2)
|
||||
/** I2S driver is frame clock slave */
|
||||
#define I2S_OPT_FRAME_CLK_SLAVE (1 << 2)
|
||||
|
||||
/** @brief Loop back mode.
|
||||
*
|
||||
* In loop back mode RX input will be connected internally to TX output.
|
||||
|
|
@ -175,6 +189,15 @@ typedef u8_t i2s_opt_t;
|
|||
*/
|
||||
#define I2S_OPT_LOOPBACK (1 << 7)
|
||||
|
||||
/** @brief Ping pong mode
|
||||
*
|
||||
* In ping pong mode TX output will keep alternating between a ping buffer
|
||||
* and a pong buffer. This is normally used in audio streams when one buffer
|
||||
* is being populated while the other is being played (DMAed) and vice versa.
|
||||
* So, in this mode, 2 sets of buffers fixed in size are used. Static Arrays
|
||||
* are used to achieve this and hence they are never freed.
|
||||
*/
|
||||
#define I2S_OPT_PINGPONG (1 << 6)
|
||||
|
||||
/**
|
||||
* @brief I2C Direction
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue