arm: remove old GDB_INFO support
That module is not used anymore: it was introduced pre-Zephyr to add some kind of awareness when debugging ARM Cortex-M3 code with GDB but was never really used by anyone. It has bitrotted, and with the recent move of the tTCS and tNANO data structures to common _kernel and k_thread, it does not even compile anymore. Jira: ZEP-1284, ZEP-951 Change-Id: Ic9afed00f4229324fe5d2aa97dc6f1c935953244 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif
Anas Nashif
parent
1f2a5791bc
commit
5ad2905532
15 changed files with 4 additions and 376 deletions
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@ -8,7 +8,6 @@ obj-y = exc_exit.o irq_init.o \
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fault_s.o isr_wrapper.o \
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fatal.o sys_fatal_error_handler.o thread_abort.o
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obj-$(CONFIG_GDB_INFO) += gdb_stub_irq_vector_table.o gdb_stub.o
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obj-$(CONFIG_CPLUSPLUS) += __aeabi_atexit.o
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obj-$(CONFIG_IRQ_OFFLOAD) += irq_offload.o
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obj-$(CONFIG_CPU_CORTEX_M) += cortex_m/
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@ -37,13 +37,6 @@ GTEXT(_ExcExit)
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GTEXT(_IntExit)
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GDATA(_kernel)
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#if CONFIG_GDB_INFO
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#define _EXIT_EXC_IF_FIBER_PREEMPTED beq _ExcExitWithGdbStub
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#else
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#define _EXIT_EXC_IF_FIBER_PREEMPTED beq _EXIT_EXC
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#endif
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#define _EXIT_EXC_IF_FIBER_NOT_READY _EXIT_EXC_IF_FIBER_PREEMPTED
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/**
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*
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* @brief Kernel housekeeping when exiting interrupt handler installed
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@ -113,8 +106,6 @@ SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, _ExcExit)
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_ExcExitWithGdbStub:
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_GDB_STUB_EXC_EXIT
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_EXIT_EXC:
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#endif /* CONFIG_PREEMPT_ENABLED */
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@ -72,8 +72,6 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__debug_monitor)
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#endif
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SECTION_SUBSEC_FUNC(TEXT,__fault,__reserved)
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_GDB_STUB_EXC_ENTRY
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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/* force unlock interrupts */
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cpsie i
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@ -109,8 +107,6 @@ _stack_frame_endif:
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push {lr}
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bl _Fault
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_GDB_STUB_EXC_EXIT
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pop {pc}
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.end
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@ -1,168 +0,0 @@
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief Extra work performed upon exception entry/exit for GDB
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*
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*
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* Prep work done when entering exceptions consists of saving the callee-saved
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* registers before they get used by exception handlers, and recording the fact
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* that we are running in an exception.
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*
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* Upon exception exit, it must be recorded that the task is not in an exception
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* anymore.
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*/
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#define _ASMLANGUAGE
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#include <offsets_short.h>
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#include <toolchain.h>
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#include <sections.h>
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#include <kernel_structs.h>
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#include <arch/cpu.h>
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_ASM_FILE_PROLOGUE
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/**
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*
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* @brief Exception entry extra work when GDB_INFO is enabled
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*
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* During normal system operation, the callee-saved registers are saved lazily
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* only when a context switch is required. To allow looking at the current
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* threads registers while debugging an exception/interrupt, they must be saved
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* upon entry since the handler could be using them: thus, looking at the CPU
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* registers would show the current system state and not the current *thread*'s
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* state.
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*
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* Also, record the fact that the thread is currently interrupted so that VQEMU
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* looks into the TCS and not the CPU registers to obtain the current thread's
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* register values.
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*
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* NOTE:
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* - must be called with interrupts locked
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* - cannot use r0 without saving it first
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, _GdbStubExcEntry)
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ldr r1, =_kernel
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ldr r2, [r1, #__tNANO_flags_OFFSET]
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/* already in an exception, do not update the registers */
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ldr r3, =EXC_ACTIVE
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ands r3, r2
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beq _GdbStubEditReg
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bx lr
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_GdbStubEditReg:
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ldr r3, =EXC_ACTIVE
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orrs r2, r3
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str r2, [r1, #__tNANO_flags_OFFSET]
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ldr r1, [r1, #__tNANO_current_OFFSET]
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str r2, [r1, #__tTCS_flags_OFFSET]
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/* save callee-saved + psp in TCS */
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adds r1, #__tTCS_preempReg_OFFSET
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mrs ip, PSP
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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/* Store current r4-r7 */
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stmea r1!, {r4-r7}
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/* copy r8-r12 into r3-r7 */
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mov r3, r8
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mov r4, r9
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mov r5, r10
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mov r6, r11
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mov r7, ip
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/* store r8-12 */
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stmea r1!, {r3-r7}
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#else /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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stmia r1, {v1-v8, ip}
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#endif
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bx lr
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/**
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*
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* @brief Exception exit extra clean up when GDB_INFO is enabled
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*
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* Record the fact that the thread is not interrupted anymore so that VQEMU
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* looks at the CPU registers and not into the TCS to obtain the current
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* thread's register values. Only do this if this is not a nested exception.
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*
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* NOTE:
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* - must be called with interrupts locked
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* - cannot use r0 without saving it first
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, _GdbStubExcExit)
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#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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/* if we're nested (ie. !RETTOBASE), do not reset EXC_ACTIVE */
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ldr r1, =_SCS_ICSR
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ldr r1, [r1]
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ands r1, #_SCS_ICSR_RETTOBASE
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it eq
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bxeq lr
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#endif
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ldr r1, =_kernel
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ldr r2, [r1, #__tNANO_flags_OFFSET]
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ldr r3, =EXC_ACTIVE
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bics r2, r3
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str r2, [r1, #__tNANO_flags_OFFSET]
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ldr r1, [r1, #__tNANO_current_OFFSET]
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str r2, [r1, #__tTCS_flags_OFFSET]
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bx lr
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/**
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*
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* @brief Stub for ISRs installed directly in vector table
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*
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* The kernel on Cortex-M3/4 can be configured so that ISRs
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* are installed directly in the vector table for maximum efficiency.
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*
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* When OS-awareness is enabled, a stub must be inserted to invoke
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* _GdbStubExcEntry() before the user ISR runs, to save the current task's
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* registers. This stub thus gets inserted in the vector table instead of the
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* user's ISR. The user's IRQ vector table gets pushed after the vector table
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* automatically by the linker script: this is all transparent to the user.
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* This stub must also act as a demuxer that find the running exception and
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* invoke the user's real ISR.
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, _irq_vector_table_entry_with_gdb_stub)
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_GDB_STUB_EXC_ENTRY
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mrs r0, IPSR /* get exception number */
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subs r0, #16 /* get IRQ number */
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ldr r1, =_irq_vector_table
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/* grab real ISR at address: r1 + (r0 << 2) (table is 4-byte wide) */
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lsls r3, r0, #2
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ldr r1, [r1, r3]
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/* jump to ISR, no return: ISR is responsible for calling _IntExit */
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bx r1
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@ -1,38 +0,0 @@
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief Stubs for IRQ part of vector table
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*
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* When GDB is enabled, the static IRQ vector table needs to install the
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* _irq_vector_table_entry_with_gdb_stub stub to do some work before calling the
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* user-installed ISRs.
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*/
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#include <toolchain.h>
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#include <sections.h>
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#include <arch/cpu.h>
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typedef void (*vth)(void); /* Vector Table Handler */
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#if defined(CONFIG_GDB_INFO) && !defined(CONFIG_SW_ISR_TABLE)
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vth __gdb_stub_irq_vector_table _irq_vector_table_with_gdb_stub[CONFIG_NUM_IRQS] = {
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[0 ...(CONFIG_NUM_IRQS - 1)] = _irq_vector_table_entry_with_gdb_stub
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};
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#endif /* CONFIG_GDB_INFO && !CONFIG_SW_ISR_TABLE */
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@ -53,8 +53,6 @@ GTEXT(_IntExit)
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*/
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SECTION_FUNC(TEXT, _isr_wrapper)
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_GDB_STUB_EXC_ENTRY
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push {lr} /* lr is now the first item on the stack */
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#ifdef CONFIG_KERNEL_EVENT_LOGGER_INTERRUPT
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@ -124,5 +122,5 @@ _idle_state_cleared:
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pop {lr}
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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/* exception return is done in _IntExit(), including _GDB_STUB_EXC_EXIT */
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/* exception return is done in _IntExit() */
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b _IntExit
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@ -55,8 +55,6 @@ GDATA(_kernel)
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SECTION_FUNC(TEXT, __pendsv)
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_GDB_STUB_EXC_ENTRY
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#ifdef CONFIG_KERNEL_EVENT_LOGGER_CONTEXT_SWITCH
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/* Register the context switch */
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push {lr}
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@ -181,8 +179,6 @@ _thread_irq_disabled:
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msr PSP, ip
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_GDB_STUB_EXC_EXIT
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/* exc return */
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bx lr
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@ -199,8 +195,6 @@ _thread_irq_disabled:
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SECTION_FUNC(TEXT, __svc)
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_GDB_STUB_EXC_ENTRY
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#if CONFIG_IRQ_OFFLOAD
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tst lr, #0x4 /* did we come from thread mode ? */
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ite eq /* if zero (equal), came from handler mode */
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@ -222,7 +216,7 @@ SECTION_FUNC(TEXT, __svc)
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blx _irq_do_offload /* call C routine which executes the offload */
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pop {lr}
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/* exception return is done in _IntExit(), including _GDB_STUB_EXC_EXIT */
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/* exception return is done in _IntExit() */
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b _IntExit
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_context_switch:
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@ -241,8 +235,6 @@ _context_switch:
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ldr r2, =_SCS_ICSR_PENDSV
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str r2, [r1, #0]
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_GDB_STUB_EXC_EXIT
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/* handler mode exit, to PendSV */
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bx lr
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#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */
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