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soc: arm: xilinx_zynqmp: Use the refactored AArch32 interrupt system

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This commit updates the `xilinx_zynqmp` platform to use the refactored
AArch32 interrupt system.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit is contained in:
Stephanos Ioannidis 2020-02-11 16:34:47 +09:00 • committed by Ioannis Glaropoulos
commit 5ac617c817
3 changed files with 1 additions and 20 deletions
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9
soc/arm/xilinx_zynqmp/Kconfig.defconfig
View file

@ -14,15 +14,6 @@ config NUM_IRQS
# - include the UART interrupts
default 220
config 2ND_LVL_ISR_TBL_OFFSET
default 1
config MAX_IRQ_PER_AGGREGATOR
default 219
config NUM_2ND_LEVEL_AGGREGATORS
default 1
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 12000000

2
soc/arm/xilinx_zynqmp/Kconfig.soc
View file

@ -8,6 +8,4 @@ config SOC_XILINX_ZYNQMP_RPU
select CPU_CORTEX_R5
select SOC_XILINX_ZYNQMP
select GIC_V1
select MULTI_LEVEL_INTERRUPTS
select 2ND_LEVEL_INTERRUPTS
select PLATFORM_SPECIFIC_INIT

10
soc/arm/xilinx_zynqmp/dts_fixup.h
View file

@ -5,12 +5,4 @@
*
*/
#undef DT_INST_0_XLNX_XUARTPS_IRQ_0
#define DT_INST_0_XLNX_XUARTPS_IRQ_0 ((DT_INST_0_XLNX_XUARTPS_IRQ_IRQ_0 + 1) << 8)
#undef DT_INST_0_CDNS_TTC_IRQ_0
#define DT_INST_0_CDNS_TTC_IRQ_0 ((DT_INST_0_CDNS_TTC_IRQ_IRQ_0 + 1) << 8)
#undef DT_INST_0_CDNS_TTC_IRQ_1
#define DT_INST_0_CDNS_TTC_IRQ_1 ((DT_INST_0_CDNS_TTC_IRQ_IRQ_1 + 1) << 8)
#undef DT_INST_0_CDNS_TTC_IRQ_2
#define DT_INST_0_CDNS_TTC_IRQ_2 ((DT_INST_0_CDNS_TTC_IRQ_IRQ_2 + 1) << 8)
/* Nothing for now */