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soc: arm: cypress: Update PSoC 6 implementation to use mtb-pdl-cat1

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Updated PSoC 6 implementation to use hal_infineon/mtb-pdl-cat1

This PR is reflected changes according to Task#1 for RFC#42883.

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
This commit is contained in:
Nazar Palamar 2022-02-28 12:23:48 +02:00 • committed by Carles Cufí
commit 5a99e93d69
4 changed files with 11 additions and 3 deletions
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3
soc/arm/cypress/psoc6/noinit.ld
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@ -15,3 +15,6 @@ KEEP(*(.heap))
. = ALIGN(4); . = ALIGN(4);
KEEP(*(.stack)) KEEP(*(.stack))
. = ALIGN(4);
KEEP(*(.cy_sharedmem))

1
soc/arm/cypress/psoc6/rwdata.ld
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@ -1,4 +1,3 @@
/* /*
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* Extracted from: * Extracted from:

8
soc/arm/cypress/psoc6/soc.c
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@ -37,6 +37,14 @@
#define CY_CFG_PWR_VDDA_MV 3300 #define CY_CFG_PWR_VDDA_MV 3300
#define CY_CFG_PWR_USING_ULP 0 #define CY_CFG_PWR_USING_ULP 0
/* Dummy symbols, requres for cy_sysint.c module.
* NOTE: in this PSoC 6 integration, PSoC 6 Zephyr drivers (uart, spi, gpio)
* do not use cy_sysint.c implementation to handle interrupt routine.
* Instead this they use IRQ_CONNECT to define ISR.
*/
uint32_t __ramVectors;
uint32_t __Vectors;
static const cy_stc_fll_manual_config_t srss_0__clock_0__fll_0__fllConfig = { static const cy_stc_fll_manual_config_t srss_0__clock_0__fll_0__fllConfig = {
.fllMult = 500u, .fllMult = 500u,
.refDiv = 20u, .refDiv = 20u,

2
soc/arm/cypress/psoc6/soc.h
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@ -19,9 +19,7 @@
#ifndef _ASMLANGUAGE #ifndef _ASMLANGUAGE
#include <cy_device_headers.h> #include <cy_device_headers.h>
#include "../common/soc_gpio.h" #include "../common/soc_gpio.h"
#include "../common/cypress_psoc6_dt.h" #include "../common/cypress_psoc6_dt.h"