diff --git a/dts/arm/st/f3/stm32f3.dtsi b/dts/arm/st/f3/stm32f3.dtsi
index 0c0ca7a0023..103df3b6550 100644
--- a/dts/arm/st/f3/stm32f3.dtsi
+++ b/dts/arm/st/f3/stm32f3.dtsi
@@ -306,6 +306,23 @@
 			label = "RTC_0";
 		};
 
+		can1: can@40006400 {
+			compatible = "st,stm32-can";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40006400 0x400>;
+			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
+			interrupt-names = "TX", "RX0", "RX1", "SCE";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			status = "disabled";
+			label = "CAN_1";
+			bus-speed = <125000>;
+			sjw = <1>;
+			prop-seg = <0>;
+			phase-seg1 = <5>;
+			phase-seg2 = <6>;
+		};
+
 		adc1: adc@50000000 {
 			compatible = "st,stm32-adc";
 			reg = <0x50000000 0x400>;
diff --git a/soc/arm/st_stm32/stm32f3/dts_fixup.h b/soc/arm/st_stm32/stm32f3/dts_fixup.h
index 47d8744bc85..c4238634bf7 100644
--- a/soc/arm/st_stm32/stm32f3/dts_fixup.h
+++ b/soc/arm/st_stm32/stm32f3/dts_fixup.h
@@ -279,4 +279,19 @@
 #define DT_ADC_1_CLOCK_BITS		DT_ST_STM32_ADC_50000000_CLOCK_BITS_0
 #define DT_ADC_1_CLOCK_BUS		DT_ST_STM32_ADC_50000000_CLOCK_BUS_0
 
+#define DT_CAN_1_BASE_ADDRESS		DT_ST_STM32_CAN_40006400_BASE_ADDRESS
+#define DT_CAN_1_BUS_SPEED		DT_ST_STM32_CAN_40006400_BUS_SPEED
+#define DT_CAN_1_NAME			DT_ST_STM32_CAN_40006400_LABEL
+#define DT_CAN_1_IRQ_TX			DT_ST_STM32_CAN_40006400_IRQ_TX
+#define DT_CAN_1_IRQ_RX0		DT_ST_STM32_CAN_40006400_IRQ_RX0
+#define DT_CAN_1_IRQ_RX1		DT_ST_STM32_CAN_40006400_IRQ_RX1
+#define DT_CAN_1_IRQ_SCE		DT_ST_STM32_CAN_40006400_IRQ_SCE
+#define DT_CAN_1_IRQ_PRIORITY		DT_ST_STM32_CAN_40006400_IRQ_0_PRIORITY
+#define DT_CAN_1_SJW			DT_ST_STM32_CAN_40006400_SJW
+#define DT_CAN_1_PROP_SEG		DT_ST_STM32_CAN_40006400_PROP_SEG
+#define DT_CAN_1_PHASE_SEG1		DT_ST_STM32_CAN_40006400_PHASE_SEG1
+#define DT_CAN_1_PHASE_SEG2		DT_ST_STM32_CAN_40006400_PHASE_SEG2
+#define DT_CAN_1_CLOCK_BUS		DT_ST_STM32_CAN_40006400_CLOCK_BUS
+#define DT_CAN_1_CLOCK_BITS		DT_ST_STM32_CAN_40006400_CLOCK_BITS
+
 /* End of SoC Level DTS fixup file */