From 5a3f528387f4684b8364e4eb90db5ebe897a4c2d Mon Sep 17 00:00:00 2001 From: Jose Alberto Meza Date: Thu, 31 Mar 2022 11:33:39 -0700 Subject: [PATCH] soc: arm: microchip: mec172x: Fix eSPI flash operations Correct eSPI flash macro so it not always results in zero, leading to eSPI flash read operation in all cases: Read, write, erase. Signed-off-by: Jose Alberto Meza --- soc/arm/microchip_mec/mec172x/reg/mec172x_espi_iom.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_espi_iom.h b/soc/arm/microchip_mec/mec172x/reg/mec172x_espi_iom.h index 2f50390d16b..8c58626d7af 100644 --- a/soc/arm/microchip_mec/mec172x/reg/mec172x_espi_iom.h +++ b/soc/arm/microchip_mec/mec172x/reg/mec172x_espi_iom.h @@ -385,7 +385,8 @@ #define MCHP_ESPI_FC_CTRL_ERS0 0x02u #define MCHP_ESPI_FC_CTRL_ERL0 0x03u #define MCHP_ESPI_FC_CTRL_FUNC(f) \ - ((uint32_t)(f) & MCHP_ESPI_FC_CTRL_FUNC_MASK) + SHLU32((uint32_t)(f), MCHP_ESPI_FC_CTRL_FUNC_POS) & \ + MCHP_ESPI_FC_CTRL_FUNC_MASK #define MCHP_ESPI_FC_CTRL_TAG_POS 4u #define MCHP_ESPI_FC_CTRL_TAG_MASK0 0x0fu