From 5a3f0b9506f8cfc32582d08e277b833b39e1e873 Mon Sep 17 00:00:00 2001 From: Yang Jialong Date: Tue, 26 Nov 2024 14:37:31 +0800 Subject: [PATCH] arch: riscv64: smp: get msip base address from dts In most implements, the msip base address is 0x2000000. But the address is not fixed in all boards. Signed-off-by: Yang Jialong --- arch/riscv/core/ipi_clint.c | 6 +++++- dts/riscv/qemu/virt-riscv.dtsi | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/riscv/core/ipi_clint.c b/arch/riscv/core/ipi_clint.c index ee9c6f2d554..e5f12566653 100644 --- a/arch/riscv/core/ipi_clint.c +++ b/arch/riscv/core/ipi_clint.c @@ -9,7 +9,11 @@ #include -#define MSIP_BASE 0x2000000UL +#define CLINT_NODE DT_NODELABEL(clint) +#if !DT_NODE_EXISTS(CLINT_NODE) +#error "Label 'clint' is not defined in the devicetree." +#endif +#define MSIP_BASE DT_REG_ADDR_RAW(CLINT_NODE) #define MSIP(hartid) ((volatile uint32_t *)MSIP_BASE)[hartid] static atomic_val_t cpu_pending_ipi[CONFIG_MP_MAX_NUM_CPUS]; diff --git a/dts/riscv/qemu/virt-riscv.dtsi b/dts/riscv/qemu/virt-riscv.dtsi index 8329a1ec62b..b810f9fe7dc 100644 --- a/dts/riscv/qemu/virt-riscv.dtsi +++ b/dts/riscv/qemu/virt-riscv.dtsi @@ -181,7 +181,7 @@ #interrupt-cells = < 0x02 >; }; - clint@2000000 { + clint: clint@2000000 { compatible = "sifive,clint0"; reg = <0x2000000 0x10000>; interrupts-extended = <&hlic0 0x03 &hlic0 0x07