boards: riscv: tlsr9518adk80d: clean-up board documentation
- Fixe reversed UART TX/RX pins info - Added info about CONFIG_FPU in case of Telink's toolchain Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
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1 changed files with 4 additions and 4 deletions
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@ -146,8 +146,8 @@ currently enabled (PORT_B for LEDs control and PORT_C for buttons) in the board
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Peripheral's pins on the SoC are mapped to the following GPIO pins in the
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``boards/riscv/tlsr9518adk80d/tlsr9518adk80d.dts`` file:
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- UART0 RX: PB2, TX: PB3
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- UART1 RX: PC6, TX: PC7
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- UART0 TX: PB2, RX: PB3
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- UART1 TX: PC6, RX: PC7
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- PWM Channel 0: PB4
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- PSPI CS0: PC4, CLK: PC5, MISO: PC6, MOSI: PC7
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- HSPI CS0: PA1, CLK: PA2, MISO: PA3, MOSI: PA4
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@ -155,8 +155,7 @@ Peripheral's pins on the SoC are mapped to the following GPIO pins in the
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Serial Port
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-----------
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The TLSR9518A SoC has 2 UARTs. The Zephyr console output is assigned
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to UART0 in the ``boards/riscv/tlsr9518adk80d/tlsr9518adk80d_defconfig`` file.
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The TLSR9518A SoC has 2 UARTs. The Zephyr console output is assigned to UART0.
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The default settings are 115200 8N1.
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Programming and debugging
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@ -174,6 +173,7 @@ the "hello_world" application.
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west build -b tlsr9518adk80d samples/hello_world
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To use `Telink RISC-V Linux Toolchain`_, ``ZEPHYR_TOOLCHAIN_VARIANT`` and ``CROSS_COMPILE`` variables need to be set.
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In addition ``CONFIG_FPU=y`` must be selected in ``boards/riscv/tlsr9518adk80d/tlsr9518adk80d_defconfig`` file.
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.. code-block:: console
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