soc: mcxn547: add support for MCXN547

Add MCXN547 support

Signed-off-by: Alexandre Rey <alexandre.rey@swisstiming.com>

soc/nxp/mcx/mcxn/Kconfig

@@ -24,6 +24,19 @@ config SOC_MCXN947_CPU0
 config SOC_MCXN947_CPU1
 	select CPU_CORTEX_M33
 
+config SOC_MCXN547
+	select CPU_CORTEX_M33
+	select CPU_HAS_ARM_SAU
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select ARMV8_M_DSP
+	select SOC_RESET_HOOK
+	select ARM_TRUSTZONE_M
+	select HAS_MCUX_CACHE
+
+config SOC_MCXN547_CPU1
+	select CPU_CORTEX_M33
+
 config SOC_MCXN236
 	select CPU_CORTEX_M33
 	select CPU_HAS_ARM_SAU
@@ -35,9 +48,10 @@ config SOC_MCXN236
 
 if SOC_SERIES_MCXN
 
-if SOC_MCXN947
+if SOC_MCXN947 || SOC_MCXN547
+
 config SECOND_CORE_MCUX
-	bool "MCXN94X's second core"
+	bool "MCXNX4X's second core"
 	depends on HAS_MCUX
 	help
 	  Indicates the second core will be enabled, and the part will run
@@ -49,11 +63,12 @@ config FLASH_DISABLE_CACHE64
 	  Disable cache64 cache.
 
 config MCUX_CORE_SUFFIX
-	default "_cm33_core0" if SOC_MCXN947_CPU0
-	default "_cm33_core1" if SOC_MCXN947_CPU1
+	default "_cm33_core0" if SOC_MCXN947_CPU0 || SOC_MCXN547_CPU0
+	default "_cm33_core1" if SOC_MCXN947_CPU1 || SOC_MCXN547_CPU1
 endif
 
 if SECOND_CORE_MCUX
+
 config SECOND_CORE_MCUX_ACCESS_LEVEL
 	int "default TrustZone access level for secondary core"
 	default 3

soc/nxp/mcx/mcxn/Kconfig.soc

@@ -20,12 +20,25 @@ config SOC_MCXN947_CPU1
 	bool
 	select SOC_MCXN947
 
+config SOC_MCXN547
+	bool
+	select SOC_SERIES_MCXN
+
+config SOC_MCXN547_CPU0
+	bool
+	select SOC_MCXN547
+
+config SOC_MCXN547_CPU1
+	bool
+	select SOC_MCXN547
+
 config SOC_MCXN236
 	bool
 	select SOC_SERIES_MCXN
 
 config SOC
 	default "mcxn947" if SOC_MCXN947
+	default "mcxn547" if SOC_MCXN547
 	default "mcxn236" if SOC_MCXN236
 
 config SOC_PART_NUMBER_MCXN947VDF
@@ -34,6 +47,12 @@ config SOC_PART_NUMBER_MCXN947VDF
 config SOC_PART_NUMBER_MCXN947VNL
 	bool
 
+config SOC_PART_NUMBER_MCXN547VDF
+	bool
+
+config SOC_PART_NUMBER_MCXN547VNL
+	bool
+
 config SOC_PART_NUMBER_MCXN236VDF
 	bool
 
@@ -43,5 +62,7 @@ config SOC_PART_NUMBER_MCXN236VNL
 config SOC_PART_NUMBER
 	default "MCXN947VDF" if SOC_PART_NUMBER_MCXN947VDF
 	default "MCXN947VNL" if SOC_PART_NUMBER_MCXN947VNL
+	default "MCXN547VDF" if SOC_PART_NUMBER_MCXN547VDF
+	default "MCXN547VNL" if SOC_PART_NUMBER_MCXN547VNL
 	default "MCXN236VDF" if SOC_PART_NUMBER_MCXN236VDF
 	default "MCXN236VNL" if SOC_PART_NUMBER_MCXN236VNL

soc/nxp/mcx/mcxn/soc.c

@@ -39,7 +39,8 @@ void soc_reset_hook(void)
  */
 DT_FOREACH_STATUS_OKAY(nxp_lpspi, FLEXCOMM_CHECK)
 
-#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_MCXN947_CPU0)
+#if defined(CONFIG_SECOND_CORE_MCUX) &&                                                            \
+	(defined(CONFIG_SOC_MCXN947_CPU0) || defined(CONFIG_SOC_MCXN547_CPU0))
 
 /* This function is also called at deep sleep resume. */
 static int second_core_boot(void)
@@ -47,8 +48,9 @@ static int second_core_boot(void)
 	/* Configure CPU1 TrustZone access level before CPU1 is enabled */
 	AHBSC->MASTER_SEC_LEVEL |=
 		AHBSC_MASTER_SEC_LEVEL_CPU1(CONFIG_SECOND_CORE_MCUX_ACCESS_LEVEL);
-	AHBSC->MASTER_SEC_ANTI_POL_REG = (~AHBSC->MASTER_SEC_LEVEL &
-		~AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) |
+	AHBSC->MASTER_SEC_ANTI_POL_REG =
+		(~AHBSC->MASTER_SEC_LEVEL &
+		 ~AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) |
 		AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(2);
 
 	/* Boot source for Core 1 from flash */

soc/nxp/mcx/soc.yml

@@ -7,6 +7,10 @@ family:
       cpuclusters:
       - name: cpu0
       - name: cpu1
+    - name: mcxn547
+      cpuclusters:
+      - name: cpu0
+      - name: cpu1
     - name: mcxn236
   - name: mcxc
     socs: