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dts: mcxa153: add dts for MCXA153

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add initial dts support(fmu, sram, syscon, gpio, port, lpuart0)
for MCXA153.

Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
This commit is contained in:
Neil Chen 2025-02-12 16:14:21 +08:00 • committed by Benjamin Cabé
commit 596d80f46f
1 changed files with 145 additions and 0 deletions
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145
dts/arm/nxp/nxp_mcxa153.dtsi Normal file
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/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <arm/armv8-m.dtsi>
#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-m33f";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
};
};
/* Dummy pinctrl node, filled with pin mux options at board level */
pinctrl: pinctrl {
compatible = "nxp,port-pinctrl";
status = "okay";
};
soc {
fmu: flash-controller@40095000 {
compatible = "nxp,msf1";
reg = <0x40095000 0x1000>;
interrupts = <12 0>;
#address-cells = <1>;
#size-cells = <1>;
flash: flash@0 {
compatible = "soc-nv-flash";
reg = <0 DT_SIZE_K(128)>;
erase-block-size = <8192>;
write-block-size = <128>;
};
};
gpio0: gpio@40102000 {
compatible = "nxp,kinetis-gpio";
status = "disabled";
reg = <0x40102000 0x1000>;
interrupts = <71 0>;
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&porta>;
};
gpio1: gpio@40103000 {
compatible = "nxp,kinetis-gpio";
status = "disabled";
reg = <0x40103000 0x1000>;
interrupts = <72 0>;
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&portb>;
};
gpio2: gpio@40104000 {
compatible = "nxp,kinetis-gpio";
status = "disabled";
reg = <0x40104000 0x1000>;
interrupts = <73 0>;
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&portc>;
};
gpio3: gpio@40105000 {
compatible = "nxp,kinetis-gpio";
status = "disabled";
reg = <0x40105000 0x1000>;
interrupts = <74 0>;
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&portd>;
};
lpuart0: lpuart@4009f000 {
compatible = "nxp,lpuart";
status = "disabled";
reg = <0x4009f000 0x1000>;
interrupts = <31 0>;
clocks = <&syscon MCUX_LPUART0_CLK>;
};
porta: pinmux@400bc000 {
compatible = "nxp,port-pinmux";
reg = <0x400bc000 0x1000>;
clocks = <&syscon MCUX_PORT0_CLK>;
};
portb: pinmux@400bd000 {
compatible = "nxp,port-pinmux";
reg = <0x400bd000 0x1000>;
clocks = <&syscon MCUX_PORT1_CLK>;
};
portc: pinmux@400be000 {
compatible = "nxp,port-pinmux";
reg = <0x400be000 0x1000>;
clocks = <&syscon MCUX_PORT2_CLK>;
};
portd: pinmux@400bf000 {
compatible = "nxp,port-pinmux";
reg = <0x400bf000 0x1000>;
clocks = <&syscon MCUX_PORT3_CLK>;
};
sramx: memory@4000000 {
compatible = "mmio-sram";
reg = <0x4000000 DT_SIZE_K(8)>;
};
sram0: memory@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(24)>;
};
syscon: syscon@40091000 {
compatible = "nxp,lpc-syscon";
reg = <0x40091000 0x4000>;
#clock-cells = <1>;
reset: reset {
compatible = "nxp,lpc-syscon-reset";
#reset-cells = <1>;
};
};
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};