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counter: nxp_s32_sys_timer: use instance-based DT macros

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At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.

The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.

Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit is contained in:
Manuel Argüelles 2023-11-07 08:44:08 +07:00 • committed by Carles Cufí
commit 595a9c11c8
2 changed files with 37 additions and 33 deletions
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15
soc/arm/nxp_s32/s32ze/soc.h
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@ -33,4 +33,19 @@
#define IP_SWT_11_BASE IP_RTU1__SWT_4_BASE
#define IP_SWT_12_BASE IP_SMU__SWT_BASE
/* STM */
#define IP_STM_0_BASE IP_CE_STM_0_BASE
#define IP_STM_1_BASE IP_CE_STM_1_BASE
#define IP_STM_2_BASE IP_CE_STM_2_BASE
#define IP_STM_3_BASE IP_RTU0__STM_0_BASE
#define IP_STM_4_BASE IP_RTU0__STM_1_BASE
#define IP_STM_5_BASE IP_RTU0__STM_2_BASE
#define IP_STM_6_BASE IP_RTU0__STM_3_BASE
#define IP_STM_7_BASE IP_RTU1__STM_0_BASE
#define IP_STM_8_BASE IP_RTU1__STM_1_BASE
#define IP_STM_9_BASE IP_RTU1__STM_2_BASE
#define IP_STM_10_BASE IP_RTU1__STM_3_BASE
#define IP_STM_11_BASE IP_SMU__STM_0_BASE
#define IP_STM_12_BASE IP_SMU__STM_2_BASE
#endif /* _NXP_S32_S32ZE_SOC_H_ */