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drivers: watchdog: sam0: initialize GCLK2 in wdt_sam0_init

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Initialize GCLK2 to output 1.024kHz required by watchdog timer.

Co-authored-by: Vlad Laba7 <vlad@laba7.com>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit is contained in:
Gerson Fernando Budke 2023-11-30 12:46:02 +02:00 • committed by Henrik Brix Andersen
commit 5903c7a669
1 changed files with 19 additions and 0 deletions
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19
soc/arm/atmel_sam0/common/soc_samd2x.c
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@ -259,6 +259,24 @@ static inline void gclk_adc_configure(void)
}
#endif
#if !CONFIG_WDT_SAM0
#define gclk_wdt_configure()
#else
static inline void gclk_wdt_configure(void)
{
GCLK->GENDIV.reg = GCLK_GENDIV_ID(2)
| GCLK_GENDIV_DIV(4);
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(2)
| GCLK_GENCTRL_GENEN
| GCLK_GENCTRL_SRC_OSCULP32K
| GCLK_GENCTRL_DIVSEL;
while (GCLK->STATUS.bit.SYNCBUSY) {
}
}
#endif
#if CONFIG_SOC_ATMEL_SAMD_OSC8M || CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN
#define osc8m_disable()
#else
@ -278,5 +296,6 @@ void z_arm_platform_init(void)
flash_waitstates_init();
gclk_main_configure();
gclk_adc_configure();
gclk_wdt_configure();
osc8m_disable();
}