drivers: watchdog: sam0: initialize GCLK2 in wdt_sam0_init
Initialize GCLK2 to output 1.024kHz required by watchdog timer. Co-authored-by: Vlad Laba7 <vlad@laba7.com> Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
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1 changed files with 19 additions and 0 deletions
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@ -259,6 +259,24 @@ static inline void gclk_adc_configure(void)
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}
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#endif
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#if !CONFIG_WDT_SAM0
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#define gclk_wdt_configure()
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#else
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static inline void gclk_wdt_configure(void)
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{
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(2)
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| GCLK_GENDIV_DIV(4);
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GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(2)
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| GCLK_GENCTRL_GENEN
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| GCLK_GENCTRL_SRC_OSCULP32K
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| GCLK_GENCTRL_DIVSEL;
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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}
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#endif
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#if CONFIG_SOC_ATMEL_SAMD_OSC8M || CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN
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#define osc8m_disable()
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#else
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@ -278,5 +296,6 @@ void z_arm_platform_init(void)
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flash_waitstates_init();
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gclk_main_configure();
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gclk_adc_configure();
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gclk_wdt_configure();
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osc8m_disable();
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}
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