boards: aesc: Add ElemRV-N

ElemRV-N is an end-to-end open-source microcontroller. This patch
adds basic support for the platform with any interfaces. They will
be added later since drivers are missing completly.

Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>

boards/aesc/elemrv/Kconfig.elemrv

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+# Copyright (c) 2025 Aesc Silicon
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ELEMRV
+	select SOC_ELEMRV_N

boards/aesc/elemrv/board.yml

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+board:
+  name: elemrv
+  full_name: ElemRV-N
+  vendor: aesc
+  socs:
+  - name: elemrv_n

boards/aesc/elemrv/doc/index.rst

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+.. zephyr:board:: elemrv
+
+Overview
+********
+
+ElemRV-N is an end-to-end open-source RISC-V microcontroller designed using SpinalHDL.
+
+Version 0.2 of ElemRV-N was successfully fabricated using `IHP's Open PDK`_, a 130nm open semiconductor process, with support from `FMD-QNC`_.
+
+For more details, refer to the official `GitHub Project`_.
+
+.. note::
+   The currently supported silicon version is ElemRV-N 0.2.
+
+Supported Features
+******************
+
+.. zephyr:board-supported-hw::
+
+System Clock
+============
+
+The system clock for the RISC-V core is set to 20 MHz. This value is specified in the ``cpu0`` devicetree node using the ``clock-frequency`` property.
+
+CPU
+===
+
+ElemRV-N integrates a VexRiscv RISC-V core featuring a 5-stage pipeline and the following ISA extensions:
+
+* M (Integer Multiply/Divide)
+* C (Compressed Instructions)
+
+It also includes the following general-purpose ``Z`` extensions:
+
+* Zicntr – Base Counter and Timer extensions
+* Zicsr – Control and Status Register operations
+* Zifencei – Instruction-fetch fence
+
+The complete ISA string for this CPU is: ``RV32IMC_Zicntr_Zicsr_Zifencei``
+
+Hart-Level Interrupt Controller (HLIC)
+======================================
+
+Each CPU core is equipped with a Hart-Level Interrupt Controller, configurable through Control and Status Registers (CSRs).
+
+Machine Timer
+=============
+
+A RISC-V compliant machine timer is enabled by default.
+
+Serial
+======
+
+The UART (Universal Asynchronous Receiver-Transmitter) interface is a configurable serial communication peripheral used for transmitting and receiving data.
+
+By default, ``uart0`` operates at a baud rate of ``115200``, which can be adjusted via the elemrv device tree.
+
+To evaluate the UART interface, build and run the following sample:
+
+.. zephyr-app-commands::
+   :board: elemrv/elemrv_n
+   :zephyr-app: samples/hello_world
+   :goals: build
+
+.. _GitHub Project:
+   https://github.com/aesc-silicon/elemrv
+
+.. _IHP's Open PDK:
+   https://github.com/IHP-GmbH/IHP-Open-PDK
+
+.. _FMD-QNC:
+   https://www.elektronikforschung.de/projekte/fmd-qnc

boards/aesc/elemrv/elemrv_elemrv_n.dts

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+/*
+ * Copyright (C) 2025 Aesc Silicon
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <aesc/elemrv-n.dtsi>
+
+/ {
+	model = "ElemRV-N";
+	compatible = "aesc,elemrv-n";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &hyperbus;
+		zephyr,flash = &flash;
+	};
+
+	soc {
+		ocram: memory@80000000 {
+			device_type = "memory";
+			compatible = "mmio-sram";
+			reg = <0x80000000 DT_SIZE_K(1)>;
+		};
+
+		hyperbus: memory@90000000 {
+			device_type = "memory";
+			compatible = "mmio-sram";
+			reg = <0x90000000 DT_SIZE_K(32)>;
+		};
+
+		flash: flash@a0010000 {
+			compatible = "soc-nv-flash";
+			reg = <0xa0010000 DT_SIZE_K(32)>;
+		};
+	};
+};
+
+&uart0 {
+	clock-frequency = <DT_FREQ_M(20)>;
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&cpu0 {
+	clock-frequency = <DT_FREQ_M(20)>;
+};

boards/aesc/elemrv/elemrv_elemrv_n.yaml

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+identifier: elemrv/elemrv_n
+name: ElemRV-N
+type: mcu
+arch: riscv
+toolchain:
+  - cross-compile
+  - zephyr
+ram: 32
+flash: 32

boards/aesc/elemrv/elemrv_elemrv_n_defconfig

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+# Copyright (c) 2025 Aesc Silicon
+# SPDX-License-Identifier: Apache-2.0
+
+# Serial Driver
+CONFIG_SERIAL=y
+
+# Enable Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y

boards/aesc/index.rst

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+.. _boards-aesc:
+
+Aesc Silicon
+############
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   **/*