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riscv: fix non-standard assembly of RISC-V

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Non-standard `jalr rd, rs` pseudo-instructions are used.
This commit changes them to `ret` for standard return pseudo-instruction
or `jalr rd, rs, 0` for no offset jump register and link.

Fixes #41100.

Signed-off-by: Henry Hsieh <r901042004@yahoo.com.tw>
This commit is contained in:
Henry Hsieh 2021-12-14 22:46:42 +08:00 • committed by Carles Cufí
commit 58d50a0e97
6 changed files with 7 additions and 7 deletions
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2
arch/riscv/core/isr.S
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@ -733,7 +733,7 @@ call_irq:
RV_OP_LOADREG t1, RV_REGSIZE(t0)
/* Call ISR function */
jalr ra, t1
jalr ra, t1, 0
on_thread_stack:
/* Get reference to _kernel */