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drivers: hwinfo: implemented hardware info support for RT11xx SOC

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RT11xx SOC uses same system reset controller as RT10xx series. Add
support for SRC on RT11xx

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2022-02-17 14:49:23 -06:00 • committed by Carles Cufí
commit 58a2b15972
6 changed files with 126 additions and 0 deletions
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1
drivers/hwinfo/CMakeLists.txt
View file

@ -13,6 +13,7 @@ zephyr_library_sources_ifdef(CONFIG_HWINFO_LITEX hwinfo_litex.c)
zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_RCM hwinfo_mcux_rcm.c)
zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SIM hwinfo_mcux_sim.c)
zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SRC hwinfo_mcux_src.c)
zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SRC_V2 hwinfo_mcux_src_rev2.c)
zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SYSCON hwinfo_mcux_syscon.c)
zephyr_library_sources_ifdef(CONFIG_HWINFO_NRF hwinfo_nrf.c)
zephyr_library_sources_ifdef(CONFIG_HWINFO_PSOC6 hwinfo_psoc6.c)

7
drivers/hwinfo/Kconfig
View file

@ -57,6 +57,13 @@ config HWINFO_MCUX_SRC
help
Enable NXP i.MX mcux SRC hwinfo driver.
config HWINFO_MCUX_SRC_V2
bool "NXP SRC reset cause (multicore devices)"
default y
depends on HAS_MCUX_SRC_V2
help
Enable version 2 multicore NXP i.MX mcux SRC hwinfo driver.
config HWINFO_MCUX_SYSCON
bool "NXP LPC device ID"
default y

101
drivers/hwinfo/hwinfo_mcux_src_rev2.c Normal file
View file

@ -0,0 +1,101 @@
/*
* Copyright (c) 2022 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_imx_src_rev2
#include <soc.h>
#include <drivers/hwinfo.h>
#include <string.h>
#include <sys/byteorder.h>
#include <fsl_soc_src.h>
#ifdef CONFIG_CPU_CORTEX_M7
#define MCUX_RESET_PIN_FLAG kSRC_M7CoreIppUserResetFlag
#define MCUX_RESET_SOFTWARE_FLAG kSRC_M7CoreM7LockUpResetFlag
#define MCUX_RESET_POR_FLAG kSRC_M7CoreIppResetFlag
#define MCUX_RESET_WATCHDOG_FLAG (kSRC_M7CoreWdogResetFlag | \
kSRC_M7CoreWdog3ResetFlag | \
kSRC_M7CoreWdog4ResetFlag)
#define MCUX_RESET_DEBUG_FLAG kSRC_M7CoreJtagResetFlag
#define MCUX_RESET_SECURITY_FLAG kSRC_M7CoreCSUResetFlag
#define MCUX_RESET_TEMPERATURE_FLAG kSRC_M7CoreTempsenseResetFlag
#define MCUX_RESET_USER_FLAG kSRC_M7CoreM7RequestResetFlag
#elif defined(CONFIG_CPU_CORTEX_M4)
#define MCUX_RESET_PIN_FLAG kSRC_M4CoreIppUserResetFlag
#define MCUX_RESET_SOFTWARE_FLAG kSRC_M4CoreM7LockUpResetFlag
#define MCUX_RESET_POR_FLAG kSRC_M4CoreIppResetFlag
#define MCUX_RESET_WATCHDOG_FLAG (kSRC_M4CoreWdogResetFlag | \
kSRC_M4CoreWdog3ResetFlag | \
kSRC_M4CoreWdog4ResetFlag)
#define MCUX_RESET_DEBUG_FLAG kSRC_M4CoreJtagResetFlag
#define MCUX_RESET_SECURITY_FLAG kSRC_M4CoreCSUResetFlag
#define MCUX_RESET_TEMPERATURE_FLAG kSRC_M4CoreTempsenseResetFlag
#define MCUX_RESET_USER_FLAG kSRC_M4CoreM7RequestResetFlag
#else
/* The SOCs currently supported have an M7 or M4 core */
#error "MCUX SRC driver not supported for this CPU!"
#endif
BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, "No nxp,imx-src compatible device found");
int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
{
uint32_t flags = 0;
uint32_t reason = SRC_GetResetStatusFlags((SRC_Type *)DT_INST_REG_ADDR(0));
if (reason & (MCUX_RESET_PIN_FLAG)) {
flags |= RESET_PIN;
}
if (reason & (MCUX_RESET_SOFTWARE_FLAG)) {
flags |= RESET_SOFTWARE;
}
if (reason & (MCUX_RESET_POR_FLAG)) {
flags |= RESET_POR;
}
if (reason & (MCUX_RESET_WATCHDOG_FLAG)) {
flags |= RESET_WATCHDOG;
}
if (reason & (MCUX_RESET_DEBUG_FLAG)) {
flags |= RESET_DEBUG;
}
if (reason & (MCUX_RESET_SECURITY_FLAG)) {
flags |= RESET_SECURITY;
}
if (reason & (MCUX_RESET_TEMPERATURE_FLAG)) {
flags |= RESET_TEMPERATURE;
}
if (reason & (MCUX_RESET_USER_FLAG)) {
flags |= RESET_USER;
}
*cause = flags;
return 0;
}
int z_impl_hwinfo_clear_reset_cause(void)
{
uint32_t reason = SRC_GetResetStatusFlags((SRC_Type *)DT_INST_REG_ADDR(0));
SRC_ClearGlobalSystemResetStatus((SRC_Type *)DT_INST_REG_ADDR(0), reason);
return 0;
}
int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
*supported = (RESET_WATCHDOG
| RESET_DEBUG
| RESET_TEMPERATURE
| RESET_PIN
| RESET_SOFTWARE
| RESET_POR
| RESET_SECURITY
| RESET_USER
);
return 0;
}