boards: soc: arm: Set zephyr,dtcm chosen node for i.mx rt boards

Sets the device tree chosen node for data tightly coupled memory (DTCM)
on i.mx rt boards that aren't already using DTCM as the chosen SRAM.
Leverages the common cortex-m linker section instead of the soc-specific
one.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
Maureen Helm 2020-10-20 21:01:04 -05:00
commit 588890faf9
6 changed files with 5 additions and 3 deletions

View file

@ -19,6 +19,7 @@
chosen { chosen {
zephyr,sram = &sdram0; zephyr,sram = &sdram0;
zephyr,dtcm = &dtcm;
zephyr,console = &lpuart1; zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1; zephyr,shell-uart = &lpuart1;
}; };

View file

@ -20,6 +20,7 @@
chosen { chosen {
zephyr,sram = &sdram0; zephyr,sram = &sdram0;
zephyr,dtcm = &dtcm;
zephyr,console = &lpuart1; zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1; zephyr,shell-uart = &lpuart1;
}; };

View file

@ -20,6 +20,7 @@
chosen { chosen {
zephyr,sram = &sdram0; zephyr,sram = &sdram0;
zephyr,dtcm = &dtcm;
zephyr,console = &lpuart1; zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1; zephyr,shell-uart = &lpuart1;
zephyr,can-primary = &flexcan2; zephyr,can-primary = &flexcan2;

View file

@ -21,6 +21,7 @@
chosen { chosen {
zephyr,sram = &sdram0; zephyr,sram = &sdram0;
zephyr,dtcm = &dtcm;
zephyr,console = &lpuart1; zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1; zephyr,shell-uart = &lpuart1;
zephyr,can-primary = &flexcan2; zephyr,can-primary = &flexcan2;

View file

@ -20,6 +20,7 @@
chosen { chosen {
zephyr,sram = &sdram0; zephyr,sram = &sdram0;
zephyr,dtcm = &dtcm;
zephyr,console = &lpuart1; zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1; zephyr,shell-uart = &lpuart1;
}; };

View file

@ -17,9 +17,6 @@ MEMORY
#if (DT_REG_SIZE(DT_NODELABEL(sdram0)) > 0) && !IS_CHOSEN_SRAM(sdram0) #if (DT_REG_SIZE(DT_NODELABEL(sdram0)) > 0) && !IS_CHOSEN_SRAM(sdram0)
SDRAM (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram0)) SDRAM (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram0))
#endif #endif
#if (DT_REG_SIZE(DT_INST(0, nxp_imx_dtcm)) > 0) && !IS_CHOSEN_SRAM(dtcm)
DTCM (wx) : ORIGIN = DT_REG_ADDR(DT_INST(0, nxp_imx_dtcm)), LENGTH = DT_REG_SIZE(DT_INST(0, nxp_imx_dtcm))
#endif
#if (DT_REG_SIZE(DT_INST(0, nxp_imx_itcm)) > 0) && !defined(CONFIG_CODE_ITCM) #if (DT_REG_SIZE(DT_INST(0, nxp_imx_itcm)) > 0) && !defined(CONFIG_CODE_ITCM)
ITCM (wx) : ORIGIN = DT_REG_ADDR(DT_INST(0, nxp_imx_itcm)), LENGTH = DT_REG_SIZE(DT_INST(0, nxp_imx_itcm)) ITCM (wx) : ORIGIN = DT_REG_ADDR(DT_INST(0, nxp_imx_itcm)), LENGTH = DT_REG_SIZE(DT_INST(0, nxp_imx_itcm))
#endif #endif