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soc: arm: viper: Add PCIe highmem OB memory in MMU table

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Add and mark PCIe highmem outbound memory as nGnRnE device memory
in Viper SoC MMU configuration.
Increase VA/PA bits to 36-bits to support the same.

Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
This commit is contained in:
Abhishek Shah 2020-07-06 01:46:51 +05:30 • committed by Carles Cufí
commit 585d6d806c
2 changed files with 13 additions and 0 deletions
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2
boards/arm/bcm958402m2_a72/bcm958402m2_a72_defconfig
View file

@ -4,6 +4,8 @@
CONFIG_SOC_SERIES_VIPER=y
CONFIG_SOC_BCM58402_A72=y
CONFIG_BOARD_BCM958402M2_A72=y
CONFIG_ARM64_VA_BITS_36=y
CONFIG_ARM64_PA_BITS_36=y
# Zephyr Kernel Configuration
CONFIG_XIP=n

11
soc/arm/bcm_vk/viper/mmu_regions.c
View file

@ -3,16 +3,27 @@
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <devicetree.h>
#include <soc.h>
#include <sys/util.h>
#include <arch/arm/aarch64/arm_mmu.h>
#define PCIE_OB_HIGHMEM_ADDR DT_REG_ADDR_BY_NAME(DT_NODELABEL(pcie0_ep), \
map_highmem)
#define PCIE_OB_HIGHMEM_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(pcie0_ep), \
map_highmem)
static const struct arm_mmu_region mmu_regions[] = {
MMU_REGION_FLAT_ENTRY("DEVICE_REGION",
0x40000000, MB(512),
MT_DEVICE_nGnRnE | MT_RW | MT_SECURE),
MMU_REGION_FLAT_ENTRY("PCIE_HIGH_OBMEM",
PCIE_OB_HIGHMEM_ADDR, PCIE_OB_HIGHMEM_SIZE,
MT_DEVICE_nGnRnE | MT_RW | MT_SECURE),
MMU_REGION_FLAT_ENTRY("DRAM0_S0",
0x60000000, MB(512),
MT_NORMAL | MT_RW | MT_SECURE),