soc: nuvoton: reg: add i3c target registers and soc functions
As title. Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
This commit is contained in:
Alvis Sun
Henrik Brix Andersen
parent
f522edb2f7
commit
578fbca78d
6 changed files with 555 additions and 145 deletions
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@ -213,16 +213,19 @@ struct scfg_reg {
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volatile uint8_t STRPST;
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/* 0x002: Reset Control and Status */
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volatile uint8_t RSTCTL;
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volatile uint8_t reserved1[3];
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volatile uint8_t reserved1;
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/* 0x004: Device Control 3*/
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volatile uint8_t DEV_CTL3;
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volatile uint8_t reserved2;
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/* 0x006: Device Control 4 */
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volatile uint8_t DEV_CTL4;
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volatile uint8_t reserved2[9];
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volatile uint8_t reserved3[9];
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/* 0x010 - 1F: Device Alternate Function 0 - F */
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volatile uint8_t DEVALT0[16];
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volatile uint8_t reserved3[6];
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volatile uint8_t reserved4[6];
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/* 0x026: Low-Voltage GPIO Pins Control 5 */
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volatile uint8_t LV_GPIO_CTL5[1];
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volatile uint8_t reserved4;
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volatile uint8_t reserved5;
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/* 0x028: Pull-Up/Pull-Down Enable 0 */
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volatile uint8_t PUPD_EN0;
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/* 0x029: Pull-Up/Pull-Down Enable 1 */
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@ -266,6 +269,12 @@ struct scfg_reg {
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#define NPCX_RSTCTL_VCC1_RST_SCRATCH 3
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#define NPCX_RSTCTL_LRESET_PLTRST_MODE 5
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#define NPCX_RSTCTL_HIPRST_MODE 6
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#define NPCX_DEV_CTL3_RNGINT_MD 1
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#define NPCX_DEV_CTL3_FVCC1_PURST_EN 2
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#define NPCX_DEV_CTL3_I3C1_MS 3
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#define NPCX_DEV_CTL3_I3C2_MS 4
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#define NPCX_DEV_CTL3_I3C3_MS 5
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#define NPCX_DEV_CTL3_SIO_CLK_SEL FIELD(6, 2)
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#define NPCX_DEV_CTL4_F_SPI_SLLK 2
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#define NPCX_DEV_CTL4_SPI_SP_SEL 4
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#define NPCX_DEV_CTL4_WP_IF 5
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@ -277,6 +286,11 @@ struct scfg_reg {
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#define NPCX_DEVPU0_I2C3_0_PUE 6
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#define NPCX_DEVPU1_F_SPI_PUD_EN 7
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#if defined(CONFIG_SOC_SERIES_NPCX4)
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/* I3C module controller, target mode for the MDMA module operation */
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#define NPCX_DEV_CTL3_I3C_MODE_BIT(inst_id) BIT(inst_id + 3)
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#endif /* End of CONFIG_SOC_SERIES_NPCX4 */
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/* Supported host interface type for HIF_TYP_SEL FILED in DEVCNT register. */
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enum npcx_hif_type {
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NPCX_HIF_TYPE_NONE,
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@ -284,6 +298,14 @@ enum npcx_hif_type {
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NPCX_HIF_TYPE_ESPI_SHI,
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};
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/* Supported VOSCCLK frequency for SIO_CLK_SEL FILED in DEV_CTL3 register. */
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enum npcx_voscclk_type {
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NPCX_VOSCCLK_96MHz,
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NPCX_VOSCCLK_100MHz,
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NPCX_VOSCCLK_120MHz,
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NPCX_VOSCCLK_90MHz,
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};
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/*
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* System Glue (GLUE) device registers
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*/
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@ -1783,7 +1805,60 @@ struct i3c_reg {
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volatile uint32_t MCONFIG;
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/* 0x004: Target Configuration */
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volatile uint32_t CONFIG;
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volatile uint32_t reserved1[31];
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/* 0x008: Target Status */
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volatile uint32_t STATUS;
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/* 0x00C: Target Control */
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volatile uint32_t CTRL;
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/* 0x010: Target Interrupt Enable Set */
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volatile uint32_t INTSET;
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/* 0x014: Target Interrupt Enable Clear */
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volatile uint32_t INTCLR;
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/* 0x018: Target Interrupt Masked */
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volatile uint32_t INTMASKED;
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/* 0x01C: Target Error and Warning */
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volatile uint32_t ERRWARN;
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/* 0x020: Target DMA Control */
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volatile uint32_t DMACTRL;
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/* 0x024-0x02B: reserved */
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volatile uint32_t reserved0[2];
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/* 0x02C: Target Data Control */
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volatile uint32_t DATACTRL;
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/* 0x030: Target Write Byte Data */
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volatile uint32_t WDATAB;
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/* 0x034: Target Write Byte Data as End */
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volatile uint32_t WDATABE;
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/* 0x038: Target Write Half-Word Data */
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volatile uint32_t WDATAH;
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/* 0x03C: Target Write Half-Word Data as End */
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volatile uint32_t WDATAHE;
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/* 0x040: Target Read Byte Data */
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volatile uint32_t RDATAB;
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/* 0x044: reserved */
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volatile uint32_t reserved1;
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/* 0x048: Target Read Half-Word Data */
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volatile uint32_t RDATAH;
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/* 0x04C-0x05B: reserved */
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volatile uint32_t reserved2[4];
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/* 0x05C: Target Capabilities 2 */
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volatile uint32_t CCAPABILITIES2;
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/* 0x060: Target Capabilities */
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volatile uint32_t CCAPABILITIES;
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/* 0x064: Target Dynamic Address */
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volatile uint32_t DYNADDR;
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/* 0x068: Target Maximum Limits */
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volatile uint32_t MAXLIMITS;
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/* 0x06C: Target Part Number */
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volatile uint32_t PARTNO;
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/* 0x070: Target ID Extension */
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volatile uint32_t IDEXT;
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/* 0x074: Target Vendor ID */
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volatile uint32_t VENDORID;
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/* 0x078: Target Timing Control Clock */
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volatile uint32_t TCCLOCK;
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/* 0x07C: Target Matching Address Index */
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volatile uint32_t MSGLAST;
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/* 0x080: reserved */
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volatile uint32_t reserved3;
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/* 0x084: Controller Control */
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volatile uint32_t MCTRL;
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/* 0x088: Controller Status */
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@ -1800,7 +1875,8 @@ struct i3c_reg {
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volatile uint32_t MERRWARN;
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/* 0x0A0: Controller DMA Control */
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volatile uint32_t MDMACTRL;
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volatile uint32_t reserved2[2];
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/* 0x0A0-0x0AB: reserved */
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volatile uint32_t reserved4[2];
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/* 0x0AC: Controller Data Control */
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volatile uint32_t MDATACTRL;
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/* 0x0B0: Controller Write Byte Data */
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@ -1813,148 +1889,315 @@ struct i3c_reg {
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volatile uint32_t MWDATAHE;
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/* 0x0C0: Controller Read Byte Data */
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volatile uint32_t MRDATAB;
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volatile uint32_t reserved3;
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/* 0x0C4: reserved */
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volatile uint32_t reserved5;
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/* 0x0C8: Controller Read Half-Word Data */
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volatile uint32_t MRDATAH;
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volatile uint32_t reserved4[3];
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/* 0x0CC-0x0D7: reserved */
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volatile uint32_t reserved6[3];
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/* 0x0D8: Start or Continue DDR Message */
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volatile uint32_t MWMSG_DDR;
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/* 0x0DC: Read DDR Message Data */
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volatile uint32_t MRMSG_DDR;
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volatile uint32_t reserved5;
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/* 0x0E0: reserved */
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volatile uint32_t reserved7;
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/* 0x0E4: Controller Dynamic Address */
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volatile uint32_t MDYNADDR;
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/* 0x0E8-0x0FF reserved */
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volatile uint32_t reserved8[6];
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/* 0x100: Target Reset Recovery Time */
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volatile uint32_t RSTACTTIME;
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/* 0x104: reserved */
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volatile uint32_t reserved9;
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/* 0x108: Target HDR Command Byte */
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volatile uint32_t HDRCMD;
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/* 0x10C-0x113: reserved */
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volatile uint32_t reserved10[2];
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/* 0x114: Target Group Definition */
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volatile uint32_t GROUPDEF;
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/* 0x118: reserved */
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volatile uint32_t reserved11;
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/* 0x11C: Target Map Control 0 */
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volatile uint32_t MAPCTRL0;
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/* 0x120: Target Map Control 1 */
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volatile uint32_t MAPCTRL1;
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/* 0x124: Target Map Control 2 */
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volatile uint32_t MAPCTRL2;
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/* 0x128: Target Map Control 3 */
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volatile uint32_t MAPCTRL3;
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/* 0x12C: Target Map Control 4 */
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volatile uint32_t MAPCTRL4;
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/* 0x130: Target Map Control 5 */
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volatile uint32_t MAPCTRL5;
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/* 0x134: Target Map Control 6 */
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volatile uint32_t MAPCTRL6;
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/* 0x138: Target Map Control 7 */
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volatile uint32_t MAPCTRL7;
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/* 0x13C: Target Map Control 8 */
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volatile uint32_t MAPCTRL8;
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/* 0x140: Target Extended IBI Data 1 */
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volatile uint32_t IBIEXT1;
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/* 0x144: Target Extended IBI Data 2 */
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volatile uint32_t IBIEXT2;
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};
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/* I3C register fields */
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#define NPCX_I3C_CONFIG_BAMATCH FIELD(16, 7)
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#define NPCX_I3C_MCONFIG_CTRENA FIELD(0, 2)
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#define NPCX_I3C_MCONFIG_DISTO 3
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#define NPCX_I3C_MCONFIG_HKEEP FIELD(4, 2) /* Must be '11' */
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#define NPCX_I3C_MCONFIG_ODSTOP 6
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#define NPCX_I3C_MCONFIG_PPBAUD FIELD(8, 4)
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#define NPCX_I3C_MCONFIG_PPLOW FIELD(12, 4)
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#define NPCX_I3C_MCONFIG_ODBAUD FIELD(16, 8)
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#define NPCX_I3C_MCONFIG_ODHPP 24
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#define NPCX_I3C_MCONFIG_SKEW FIELD(25, 3)
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#define NPCX_I3C_MCONFIG_I2CBAUD FIELD(28, 4)
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#define NPCX_I3C_MCTRL_REQUEST FIELD(0, 3)
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#define NPCX_I3C_MCTRL_TYPE FIELD(4, 2)
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#define NPCX_I3C_MCTRL_IBIRESP FIELD(6, 2)
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#define NPCX_I3C_MCTRL_DIR 8
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#define NPCX_I3C_MCTRL_ADDR FIELD(9, 7)
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#define NPCX_I3C_MCTRL_RDTERM FIELD(16, 8)
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#define NPCX_I3C_MSTATUS_STATE FIELD(0, 3)
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#define NPCX_I3C_MSTATUS_BETWEEN 4
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#define NPCX_I3C_MSTATUS_NACKED 5
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#define NPCX_I3C_MSTATUS_IBITYPE FIELD(6, 2)
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#define NPCX_I3C_MSTATUS_TGTSTART 8
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#define NPCX_I3C_MSTATUS_MCTRLDONE 9
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#define NPCX_I3C_MSTATUS_COMPLETE 10
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#define NPCX_I3C_MSTATUS_RXPEND 11
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#define NPCX_I3C_MSTATUS_TXNOTFULL 12
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#define NPCX_I3C_MSTATUS_IBIWON 13
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#define NPCX_I3C_MSTATUS_ERRWARN 15
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#define NPCX_I3C_MSTATUS_NOWCNTLR 19
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#define NPCX_I3C_MSTATUS_IBIADDR FIELD(24, 7)
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#define NPCX_I3C_IBIRULES_MSB0 30
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#define NPCX_I3C_IBIRULES_NOBYTE 31
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#define NPCX_I3C_MINTSET_TGTSTART 8
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#define NPCX_I3C_MINTSET_MCTRLDONE 9
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#define NPCX_I3C_MINTSET_COMPLETE 10
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#define NPCX_I3C_MINTSET_RXPEND 11
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#define NPCX_I3C_MINTSET_TXNOTFULL 12
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#define NPCX_I3C_MINTSET_IBIWON 13
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#define NPCX_I3C_MINTSET_ERRWARN 15
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#define NPCX_I3C_MINTSET_NOWCNTLR 19
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#define NPCX_I3C_MINTCLR_TGTSTART 8
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#define NPCX_I3C_MINTCLR_MCTRLDONE 9
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#define NPCX_I3C_MINTCLR_COMPLETE 10
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#define NPCX_I3C_MINTCLR_RXPEND 11
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#define NPCX_I3C_MINTCLR_TXNOTFULL 12
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#define NPCX_I3C_MINTCLR_IBIWON 13
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#define NPCX_I3C_MINTCLR_ERRWARN 15
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#define NPCX_I3C_MINTCLR_NOWCNTLR 19
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#define NPCX_I3C_MDATACTRL_FLUSHTB 0
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#define NPCX_I3C_MDATACTRL_FLUSHFB 1
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#define NPCX_I3C_MDATACTRL_UNLOCK 3
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#define NPCX_I3C_MDATACTRL_TXTRIG FIELD(4, 2)
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#define NPCX_I3C_MDATACTRL_RXTRIG FIELD(6, 2)
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#define NPCX_I3C_MDATACTRL_TXCOUNT FIELD(16, 5)
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#define NPCX_I3C_MDATACTRL_RXCOUNT FIELD(24, 5)
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#define NPCX_I3C_MDATACTRL_TXFULL 30
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#define NPCX_I3C_MDATACTRL_RXEMPTY 31
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#define NPCX_I3C_MERRWARN_NACK 2
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#define NPCX_I3C_MERRWARN_WRABT 3
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#define NPCX_I3C_MERRWARN_TERM 4
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#define NPCX_I3C_MERRWARN_HPAR 9
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#define NPCX_I3C_MERRWARN_HCRC 10
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#define NPCX_I3C_MERRWARN_OREAD 16
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#define NPCX_I3C_MERRWARN_OWRITE 17
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#define NPCX_I3C_MERRWARN_MSGERR 18
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#define NPCX_I3C_MERRWARN_INVERQ 19
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#define NPCX_I3C_MERRWARN_TIMEOUT 20
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#define NPCX_I3C_MDMACTRL_DMAFB FIELD(0, 2)
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#define NPCX_I3C_MDMACTRL_DMATB FIELD(2, 2)
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/* I3C controller register fields */
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#define NPCX_I3C_MCONFIG_CTRENA FIELD(0, 2)
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#define NPCX_I3C_MCONFIG_DISTO 3
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#define NPCX_I3C_MCONFIG_HKEEP FIELD(4, 2) /* Must be '11' */
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#define NPCX_I3C_MCONFIG_ODSTOP 6
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#define NPCX_I3C_MCONFIG_PPBAUD FIELD(8, 4)
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#define NPCX_I3C_MCONFIG_PPLOW FIELD(12, 4)
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#define NPCX_I3C_MCONFIG_ODBAUD FIELD(16, 8)
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#define NPCX_I3C_MCONFIG_ODHPP 24
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#define NPCX_I3C_MCONFIG_SKEW FIELD(25, 3)
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#define NPCX_I3C_MCONFIG_I2CBAUD FIELD(28, 4)
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#define NPCX_I3C_MCTRL_REQUEST FIELD(0, 3)
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#define NPCX_I3C_MCTRL_TYPE FIELD(4, 2)
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#define NPCX_I3C_MCTRL_IBIRESP FIELD(6, 2)
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#define NPCX_I3C_MCTRL_DIR 8
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#define NPCX_I3C_MCTRL_ADDR FIELD(9, 7)
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#define NPCX_I3C_MCTRL_RDTERM FIELD(16, 8)
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#define NPCX_I3C_MSTATUS_STATE FIELD(0, 3)
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#define NPCX_I3C_MSTATUS_BETWEEN 4
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#define NPCX_I3C_MSTATUS_NACKED 5
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#define NPCX_I3C_MSTATUS_IBITYPE FIELD(6, 2)
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#define NPCX_I3C_MSTATUS_TGTSTART 8
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#define NPCX_I3C_MSTATUS_MCTRLDONE 9
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#define NPCX_I3C_MSTATUS_COMPLETE 10
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#define NPCX_I3C_MSTATUS_RXPEND 11
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#define NPCX_I3C_MSTATUS_TXNOTFULL 12
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#define NPCX_I3C_MSTATUS_IBIWON 13
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#define NPCX_I3C_MSTATUS_ERRWARN 15
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#define NPCX_I3C_MSTATUS_NOWCNTLR 19
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#define NPCX_I3C_MSTATUS_IBIADDR FIELD(24, 7)
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#define NPCX_I3C_IBIRULES_MSB0 30
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#define NPCX_I3C_IBIRULES_NOBYTE 31
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#define NPCX_I3C_MINTSET_TGTSTART 8
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#define NPCX_I3C_MINTSET_MCTRLDONE 9
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#define NPCX_I3C_MINTSET_COMPLETE 10
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#define NPCX_I3C_MINTSET_RXPEND 11
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#define NPCX_I3C_MINTSET_TXNOTFULL 12
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#define NPCX_I3C_MINTSET_IBIWON 13
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#define NPCX_I3C_MINTSET_ERRWARN 15
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#define NPCX_I3C_MINTSET_NOWCNTLR 19
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#define NPCX_I3C_MINTCLR_TGTSTART 8
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#define NPCX_I3C_MINTCLR_MCTRLDONE 9
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#define NPCX_I3C_MINTCLR_COMPLETE 10
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#define NPCX_I3C_MINTCLR_RXPEND 11
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#define NPCX_I3C_MINTCLR_TXNOTFULL 12
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#define NPCX_I3C_MINTCLR_IBIWON 13
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#define NPCX_I3C_MINTCLR_ERRWARN 15
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#define NPCX_I3C_MINTCLR_NOWCNTLR 19
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#define NPCX_I3C_MINTMASKED_NOWCNTLR 19
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#define NPCX_I3C_MDATACTRL_FLUSHTB 0
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#define NPCX_I3C_MDATACTRL_FLUSHFB 1
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#define NPCX_I3C_MDATACTRL_UNLOCK 3
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#define NPCX_I3C_MDATACTRL_TXTRIG FIELD(4, 2)
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#define NPCX_I3C_MDATACTRL_RXTRIG FIELD(6, 2)
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#define NPCX_I3C_MDATACTRL_TXCOUNT FIELD(16, 5)
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#define NPCX_I3C_MDATACTRL_RXCOUNT FIELD(24, 5)
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#define NPCX_I3C_MDATACTRL_TXFULL 30
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#define NPCX_I3C_MDATACTRL_RXEMPTY 31
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#define NPCX_I3C_MERRWARN_NACK 2
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#define NPCX_I3C_MERRWARN_WRABT 3
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#define NPCX_I3C_MERRWARN_TERM 4
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#define NPCX_I3C_MERRWARN_HPAR 9
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#define NPCX_I3C_MERRWARN_HCRC 10
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#define NPCX_I3C_MERRWARN_OREAD 16
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#define NPCX_I3C_MERRWARN_OWRITE 17
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#define NPCX_I3C_MERRWARN_MSGERR 18
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#define NPCX_I3C_MERRWARN_INVERQ 19
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#define NPCX_I3C_MERRWARN_TIMEOUT 20
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#define NPCX_I3C_MDMACTRL_DMAFB FIELD(0, 2)
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#define NPCX_I3C_MDMACTRL_DMATB FIELD(2, 2)
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/* MCONFIG options */
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#define MCONFIG_CTRENA_OFF 0x0
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#define MCONFIG_CTRENA_ON 0x1
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#define MCONFIG_CTRENA_CAPABLE 0x2
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#define MCONFIG_HKEEP_EXT_SDA_SCL 0x3
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/* MCTRL options */
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#define MCTRL_REQUEST_NONE 0 /* None */
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#define MCTRL_REQUEST_EMITSTARTADDR 1 /* Emit a START */
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#define MCTRL_REQUEST_EMITSTOP 2 /* Emit a STOP */
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#define MCTRL_REQUEST_IBIACKNACK 3 /* Manually ACK or NACK an IBI */
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#define MCTRL_REQUEST_PROCESSDAA 4 /* Starts the DAA process */
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#define MCTRL_REQUEST_FORCEEXIT 6 /* Emit HDR Exit Pattern */
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/* Emits a START with address 7Eh when a slave pulls I3C_SDA low to request an IBI */
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#define MCTRL_REQUEST_AUTOIBI 7
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|
||||
/* ACK with mandatory byte determined by IBIRULES or ACK with no mandatory byte */
|
||||
#define MCTRL_IBIRESP_ACK 0
|
||||
#define MCTRL_IBIRESP_NACK 1 /* NACK */
|
||||
#define MCTRL_IBIRESP_ACK_MANDATORY 2 /* ACK with mandatory byte */
|
||||
#define MCTRL_IBIRESP_MANUAL 3
|
||||
|
||||
/* For REQUEST = EmitStartAddr */
|
||||
enum npcx_i3c_mctrl_type {
|
||||
NPCX_I3C_MCTRL_TYPE_I3C,
|
||||
NPCX_I3C_MCTRL_TYPE_I2C,
|
||||
NPCX_I3C_MCTRL_TYPE_I3C_HDR_DDR,
|
||||
};
|
||||
|
||||
/* For REQUEST = ForceExit/Target Reset */
|
||||
#define MCTRL_TYPE_HDR_EXIT 0
|
||||
#define MCTRL_TYPE_TGT_RESTART 2
|
||||
|
||||
/* MSTATUS options */
|
||||
#define MSTATUS_STATE_IDLE 0x0
|
||||
#define MSTATUS_STATE_TGTREQ 0x1
|
||||
#define MSTATUS_STATE_NORMACT 0x3 /* SDR message mode */
|
||||
#define MSTATUS_STATE_MSGDDR 0x4
|
||||
#define MSTATUS_STATE_DAA 0x5
|
||||
#define MSTATUS_STATE_IBIACK 0x6
|
||||
#define MSTATUS_STATE_IBIRCV 0x7
|
||||
#define MSTATUS_IBITYPE_NONE 0x0
|
||||
#define MSTATUS_IBITYPE_IBI 0x1
|
||||
#define MSTATUS_IBITYPE_CR 0x2
|
||||
#define MSTATUS_IBITYPE_HJ 0x3
|
||||
|
||||
/* IBIRULES */
|
||||
#define IBIRULES_ADDR_MSK 0x3F
|
||||
#define IBIRULES_ADDR_SHIFT 0x6
|
||||
|
||||
/* MDMACTRL options */
|
||||
#define MDMA_DMAFB_DISABLE 0x0
|
||||
#define MDMA_DMAFB_EN_ONE_FRAME 0x1
|
||||
#define MDMA_DMAFB_EN_MANUAL 0x2
|
||||
#define MDMA_DMATB_DISABLE 0x0
|
||||
#define MDMA_DMATB_EN_ONE_FRAME 0x1
|
||||
#define MDMA_DMATB_EN_MANUAL 0x2
|
||||
/* I3C target register fields */
|
||||
#define NPCX_I3C_CONFIG_TGTENA 0
|
||||
#define NPCX_I3C_CONFIG_MATCHSS 2
|
||||
#define NPCX_I3C_CONFIG_S0IGNORE 3
|
||||
#define NPCX_I3C_CONFIG_IDRAND 8
|
||||
#define NPCX_I3C_CONFIG_OFFLINE 9
|
||||
#define NPCX_I3C_CONFIG_HDRCMD FIELD(10, 2)
|
||||
#define NPCX_I3C_CONFIG_BAMATCH FIELD(16, 7)
|
||||
#define NPCX_I3C_CONFIG_SADDR FIELD(25, 7)
|
||||
#define NPCX_I3C_STATUS_STNOTSTOP 0
|
||||
#define NPCX_I3C_STATUS_STMSG 1
|
||||
#define NPCX_I3C_STATUS_STCCCH 2
|
||||
#define NPCX_I3C_STATUS_STREQRD 3
|
||||
#define NPCX_I3C_STATUS_STREQWR 4
|
||||
#define NPCX_I3C_STATUS_STDAA 5
|
||||
#define NPCX_I3C_STATUS_STHDR 6
|
||||
#define NPCX_I3C_STATUS_START 8
|
||||
#define NPCX_I3C_STATUS_MATCHED 9
|
||||
#define NPCX_I3C_STATUS_STOP 10
|
||||
#define NPCX_I3C_STATUS_RXPEND 11
|
||||
#define NPCX_I3C_STATUS_TXNOTFULL 12
|
||||
#define NPCX_I3C_STATUS_DACHG 13
|
||||
#define NPCX_I3C_STATUS_CCC 14
|
||||
#define NPCX_I3C_STATUS_ERRWARN 15
|
||||
#define NPCX_I3C_STATUS_HDRMATCH 16
|
||||
#define NPCX_I3C_STATUS_CHANDLED 17
|
||||
#define NPCX_I3C_STATUS_EVENT 18
|
||||
#define NPCX_I3C_STATUS_TGTRST 19
|
||||
#define NPCX_I3C_STATUS_EVDET FIELD(20, 2)
|
||||
#define NPCX_I3C_STATUS_IBIDIS 24
|
||||
#define NPCX_I3C_STATUS_MRDIS 25
|
||||
#define NPCX_I3C_STATUS_HJDIS 27
|
||||
#define NPCX_I3C_STATUS_ACTSTATE FIELD(28, 2)
|
||||
#define NPCX_I3C_STATUS_TIMECTRL FIELD(30, 2)
|
||||
#define NPCX_I3C_CTRL_EVENT FIELD(0, 2)
|
||||
#define NPCX_I3C_CTRL_EXTDATA 3
|
||||
#define NPCX_I3C_CTRL_MAPIDX FIELD(4, 4)
|
||||
#define NPCX_I3C_CTRL_IBIDATA FIELD(8, 8)
|
||||
#define NPCX_I3C_CTRL_PENDINT FIELD(16, 4)
|
||||
#define NPCX_I3C_CTRL_ACTSTATE FIELD(20, 2)
|
||||
#define NPCX_I3C_CTRL_VENDINFO FIELD(24, 8)
|
||||
#define NPCX_I3C_INTSET_START 8
|
||||
#define NPCX_I3C_INTSET_MATCHED 9
|
||||
#define NPCX_I3C_INTSET_STOP 10
|
||||
#define NPCX_I3C_INTSET_RXPEND 11
|
||||
#define NPCX_I3C_INTSET_TXNOTFULL 12
|
||||
#define NPCX_I3C_INTSET_DACHG 13
|
||||
#define NPCX_I3C_INTSET_CCC 14
|
||||
#define NPCX_I3C_INTSET_ERRWARN 15
|
||||
#define NPCX_I3C_INTSET_HDRMATCH 16
|
||||
#define NPCX_I3C_INTSET_CHANDLED 17
|
||||
#define NPCX_I3C_INTSET_EVENT 18
|
||||
#define NPCX_I3C_INTSET_TGTRST 19
|
||||
#define NPCX_I3C_INTCLR_START 8
|
||||
#define NPCX_I3C_INTCLR_MATCHED 9
|
||||
#define NPCX_I3C_INTCLR_STOP 10
|
||||
#define NPCX_I3C_INTCLR_RXPEND 11
|
||||
#define NPCX_I3C_INTCLR_TXNOTFULL 12
|
||||
#define NPCX_I3C_INTCLR_DACHG 13
|
||||
#define NPCX_I3C_INTCLR_CCC 14
|
||||
#define NPCX_I3C_INTCLR_ERRWARN 15
|
||||
#define NPCX_I3C_INTCLR_HDRMATCH 16
|
||||
#define NPCX_I3C_INTCLR_CHANDLED 17
|
||||
#define NPCX_I3C_INTCLR_EVENT 18
|
||||
#define NPCX_I3C_INTCLR_TGTRST 19
|
||||
#define NPCX_I3C_INTMASKED_START 8
|
||||
#define NPCX_I3C_INTMASKED_MATCHED 9
|
||||
#define NPCX_I3C_INTMASKED_STOP 10
|
||||
#define NPCX_I3C_INTMASKED_RXPEND 11
|
||||
#define NPCX_I3C_INTMASKED_TXNOTFULL 12
|
||||
#define NPCX_I3C_INTMASKED_DACHG 13
|
||||
#define NPCX_I3C_INTMASKED_CCC 14
|
||||
#define NPCX_I3C_INTMASKED_ERRWARN 15
|
||||
#define NPCX_I3C_INTMASKED_HDRMATCH 16
|
||||
#define NPCX_I3C_INTMASKED_CHANDLED 17
|
||||
#define NPCX_I3C_INTMASKED_EVENT 18
|
||||
#define NPCX_I3C_INTMASKED_TGTRST 19
|
||||
#define NPCX_I3C_ERRWARN_ORUN 0
|
||||
#define NPCX_I3C_ERRWARN_URUN 1
|
||||
#define NPCX_I3C_ERRWARN_URUNNACK 2
|
||||
#define NPCX_I3C_ERRWARN_TERM 3
|
||||
#define NPCX_I3C_ERRWARN_INVSTART 4
|
||||
#define NPCX_I3C_ERRWARN_SPAR 8
|
||||
#define NPCX_I3C_ERRWARN_HPAR 9
|
||||
#define NPCX_I3C_ERRWARN_HCRC 10
|
||||
#define NPCX_I3C_ERRWARN_S0S1 11
|
||||
#define NPCX_I3C_ERRWARN_OREAD 16
|
||||
#define NPCX_I3C_ERRWARN_OWRITE 17
|
||||
#define NPCX_I3C_DMACTRL_DMAFB FIELD(0, 2)
|
||||
#define NPCX_I3C_DMACTRL_DMATB FIELD(2, 2)
|
||||
#define NPCX_I3C_DATACTRL_FLUSHTB 0
|
||||
#define NPCX_I3C_DATACTRL_FLUSHFB 1
|
||||
#define NPCX_I3C_DATACTRL_UNLOCK 3
|
||||
#define NPCX_I3C_DATACTRL_TXTRIG FIELD(4, 2)
|
||||
#define NPCX_I3C_DATACTRL_RXTRIG FIELD(6, 2)
|
||||
#define NPCX_I3C_DATACTRL_TXCOUNT FIELD(16, 6)
|
||||
#define NPCX_I3C_DATACTRL_RXCOUNT FIELD(24, 6)
|
||||
#define NPCX_I3C_DATACTRL_TXFULL 30
|
||||
#define NPCX_I3C_DATACTRL_RXEMPTY 31
|
||||
#define NPCX_I3C_WDATAB_DATA FIELD(0, 8)
|
||||
#define NPCX_I3C_WDATAB_END_B 8
|
||||
#define NPCX_I3C_WDATAB_END_A 16
|
||||
#define NPCX_I3C_WDATABE_DATA FIELD(0, 8)
|
||||
#define NPCX_I3C_WDATAH_DATA0 FIELD(0, 8)
|
||||
#define NPCX_I3C_WDATAH_DATA1 FIELD(8, 8)
|
||||
#define NPCX_I3C_WDATAH_END 16
|
||||
#define NPCX_I3C_WDATAHE_DATA0 FIELD(0, 8)
|
||||
#define NPCX_I3C_WDATAHE_DATA1 FIELD(8, 8)
|
||||
#define NPCX_I3C_RDATAB_DATA FIELD(0, 8)
|
||||
#define NPCX_I3C_RDATAH_DATA0 FIELD(0, 8)
|
||||
#define NPCX_I3C_RDATAH_DATA1 FIELD(8, 8)
|
||||
#define NPCX_I3C_CAPABILITIES2_MAPCNT FIELD(0, 4)
|
||||
#define NPCX_I3C_CAPABILITIES2_I2C10B 4
|
||||
#define NPCX_I3C_CAPABILITIES2_I2CRST 5
|
||||
#define NPCX_I3C_CAPABILITIES2_I2CDEVID 6
|
||||
#define NPCX_I3C_CAPABILITIES2_DATA32 7
|
||||
#define NPCX_I3C_CAPABILITIES2_IBIEXT 8
|
||||
#define NPCX_I3C_CAPABILITIES2_IBIXREG 9
|
||||
#define NPCX_I3C_CAPABILITIES2_SMLANE FIELD(12, 2)
|
||||
#define NPCX_I3C_CAPABILITIES2_V1_1 16
|
||||
#define NPCX_I3C_CAPABILITIES2_TGTRST 17
|
||||
#define NPCX_I3C_CAPABILITIES2_GROUP FIELD(18, 2)
|
||||
#define NPCX_I3C_CAPABILITIES2_AASA 21
|
||||
#define NPCX_I3C_CAPABILITIES2_SSTSUB 22
|
||||
#define NPCX_I3C_CAPABILITIES2_SSTWR 23
|
||||
#define NPCX_I3C_CAPABILITIES_IDENA FIELD(0, 2)
|
||||
#define NPCX_I3C_CAPABILITIES_IDREG FIELD(2, 4)
|
||||
#define NPCX_I3C_CAPABILITIES_HDRSUPP FIELD(6, 3)
|
||||
#define NPCX_I3C_CAPABILITIES_CNTLR 9
|
||||
#define NPCX_I3C_CAPABILITIES_SADDR FIELD(10, 2)
|
||||
#define NPCX_I3C_CAPABILITIES_CCCHANDLE FIELD(12, 4)
|
||||
#define NPCX_I3C_CAPABILITIES_IBI_MR_HJ FIELD(16, 5)
|
||||
#define NPCX_I3C_CAPABILITIES_TIMECTRL 21
|
||||
#define NPCX_I3C_CAPABILITIES_EXTFIFO FIELD(23, 3)
|
||||
#define NPCX_I3C_CAPABILITIES_FIFOTX FIELD(26, 2)
|
||||
#define NPCX_I3C_CAPABILITIES_FIFORX FIELD(28, 2)
|
||||
#define NPCX_I3C_CAPABILITIES_INT 30
|
||||
#define NPCX_I3C_CAPABILITIES_DMA 31
|
||||
#define NPCX_I3C_DYNADDR_DAVALID 0
|
||||
#define NPCX_I3C_DYNADDR_DADDR FIELD(1, 7)
|
||||
#define NPCX_I3C_DYNADDR_CAUSE FIELD(8, 3)
|
||||
#define NPCX_I3C_MAXLIMITS_MAXRD FIELD(0, 12)
|
||||
#define NPCX_I3C_MAXLIMITS_MAXWR FIELD(16, 12)
|
||||
#define NPCX_I3C_IDEXT_DCR FIELD(8, 8)
|
||||
#define NPCX_I3C_IDEXT_BCR FIELD(16, 8)
|
||||
#define NPCX_I3C_VENDORID_VID FIELD(0, 15)
|
||||
#define NPCX_I3C_TCCLOCK_ACCURACY FIELD(0, 8)
|
||||
#define NPCX_I3C_TCCLOCK_FREQ FIELD(8, 8)
|
||||
#define NPCX_I3C_MSGLAST_MAPLAST FIELD(0, 4)
|
||||
#define NPCX_I3C_MSGLAST_LASTSTATIC 4
|
||||
#define NPCX_I3C_MSGLAST_LASTGROUP 5
|
||||
#define NPCX_I3C_MSGLAST_LASTMODE FIELD(6, 2)
|
||||
#define NPCX_I3C_MSGLAST_MAPLASTM1 FIELD(8, 4)
|
||||
#define NPCX_I3C_MSGLAST_LASTGROUPM1 13
|
||||
#define NPCX_I3C_MSGLAST_LASTMODE1 FIELD(14, 2)
|
||||
#define NPCX_I3C_MSGLAST_MAPLASTM2 FIELD(16, 4)
|
||||
#define NPCX_I3C_MSGLAST_LASTGROUPM2 21
|
||||
#define NPCX_I3C_MSGLAST_LASTMODE2 FIELD(22, 2)
|
||||
#define NPCX_I3C_RSTACTTIME_PERRSTTIM FIELD(0, 8)
|
||||
#define NPCX_I3C_RSTACTTIME_SYSRSTTIM FIELD(8, 8)
|
||||
#define NPCX_I3C_HDRCMD_CMD0 FIELD(0, 8)
|
||||
#define NPCX_I3C_HDRCMD_OVFL 30
|
||||
#define NPCX_I3C_HDRCMD_NEWCMD 31
|
||||
#define NPCX_I3C_GROUPDEF_GRP0ENA 0
|
||||
#define NPCX_I3C_GROUPDEF_GRP0DA FIELD(1, 7)
|
||||
#define NPCX_I3C_GROUPDEF_GRP1ENA 8
|
||||
#define NPCX_I3C_GROUPDEF_GRP1DA FIELD(9, 7)
|
||||
#define NPCX_I3C_GROUPDEF_GRP2ENA 16
|
||||
#define NPCX_I3C_GROUPDEF_GRP2DA FIELD(17, 7)
|
||||
#define NPCX_I3C_MAPCTRL0_ENA 0
|
||||
#define NPCX_I3C_MAPCTRL0_DA FIELD(1, 7)
|
||||
#define NPCX_I3C_MAPCTRL0_CAUSE FIELD(8, 3)
|
||||
#define NPCX_I3C_MAPCTRLn_ENA 0
|
||||
#define NPCX_I3C_MAPCTRLn_ADDR FIELD(1, 7)
|
||||
#define NPCX_I3C_MAPCTRLn_MAPSA 8
|
||||
#define NPCX_I3C_MAPCTRLn_NACK 12
|
||||
#define NPCX_I3C_MAPCTRLn_AUTO 13
|
||||
#define NPCX_I3C_MAPCTRLn_SLOT_PID FIELD(14, 5)
|
||||
#define NPCX_I3C_IBIEXT1_CNT FIELD(0, 3)
|
||||
#define NPCX_I3C_IBIEXT1_EXT1 FIELD(8, 8)
|
||||
#define NPCX_I3C_IBIEXT1_EXT2 FIELD(16, 8)
|
||||
#define NPCX_I3C_IBIEXT1_EXT3 FIELD(24, 8)
|
||||
#define NPCX_I3C_IBIEXT2_EXT4 FIELD(0, 8)
|
||||
#define NPCX_I3C_IBIEXT2_EXT5 FIELD(8, 8)
|
||||
#define NPCX_I3C_IBIEXT2_EXT6 FIELD(16, 8)
|
||||
#define NPCX_I3C_IBIEXT2_EXT7 FIELD(24, 8)
|
||||
|
||||
/* MDMA Controller registers */
|
||||
struct mdma_reg {
|
||||
|
|
@ -1994,11 +2237,16 @@ struct mdma_reg {
|
|||
};
|
||||
|
||||
/* MDMA register fields */
|
||||
#define NPCX_MDMA_CTL_MDMAEN 0
|
||||
#define NPCX_MDMA_CTL_MPD 1
|
||||
#define NPCX_MDMA_CTL_SIEN 8
|
||||
#define NPCX_MDMA_CTL_MPS 14
|
||||
#define NPCX_MDMA_CTL_TC 18
|
||||
#define NPCX_MDMA_TCNT_TFR_CNT FIELD(0, 12)
|
||||
#define NPCX_MDMA_CTL_MDMAEN 0
|
||||
#define NPCX_MDMA_CTL_MPD 1
|
||||
#define NPCX_MDMA_CTL_SIEN 8
|
||||
#define NPCX_MDMA_CTL_MPS 14
|
||||
#define NPCX_MDMA_CTL_TC 18
|
||||
|
||||
/* Channel 0/1 Transfer Count Register (MDMA_TCNT0/MDMA_TCNT1) */
|
||||
#define NPCX_MDMA_TCNT_TFR_CNT FIELD(0, 13)
|
||||
|
||||
/* Channel 0/1 Current Transfer Count Register (MDMA_CTCNT0/MDMA_CTCNT1) */
|
||||
#define NPCX_MDMA_CTCNT_CURRENT_TFR_CNT FIELD(0, 13)
|
||||
|
||||
#endif /* _NUVOTON_NPCX_REG_DEF_H */
|
||||
|
|
|
|||
|
|
@ -199,8 +199,8 @@ NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[2], 0x00c);
|
|||
NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[3], 0x010);
|
||||
|
||||
/* I3C register structure check */
|
||||
NPCX_REG_SIZE_CHECK(i3c_reg, 0x0E8);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, MCONFIG, 0x000);
|
||||
NPCX_REG_SIZE_CHECK(i3c_reg, 0x148);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, MCONFIG, 0x000); /* Controller register */
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, MCTRL, 0x084);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, IBIRULES, 0x08C);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, MINTSET, 0x090);
|
||||
|
|
@ -217,6 +217,16 @@ NPCX_REG_OFFSET_CHECK(i3c_reg, MRDATAH, 0x0C8);
|
|||
NPCX_REG_OFFSET_CHECK(i3c_reg, MWMSG_DDR, 0x0D8);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, MRMSG_DDR, 0x0DC);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, MDYNADDR, 0x0E4);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, CONFIG, 0x004); /* Target register */
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, STATUS, 0x008);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, CTRL, 0x00C);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, INTSET, 0x010);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, INTCLR, 0x014);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, INTMASKED, 0x018);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, ERRWARN, 0x01C);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, DMACTRL, 0x020);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, DATACTRL, 0x02C);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, IBIEXT2, 0x144);
|
||||
|
||||
/* MDMA register structure check */
|
||||
NPCX_REG_SIZE_CHECK(mdma_reg, 0x03C);
|
||||
|
|
|
|||
|
|
@ -131,6 +131,21 @@ void npcx_host_interface_sel(enum npcx_hif_type hif_type)
|
|||
SET_FIELD(inst_scfg->DEVCNT, NPCX_DEVCNT_HIF_TYP_SEL_FIELD, hif_type);
|
||||
}
|
||||
|
||||
void npcx_i3c_target_sel(uint8_t module_id, bool enable)
|
||||
{
|
||||
#if defined(CONFIG_SOC_SERIES_NPCX4)
|
||||
struct scfg_reg *inst_scfg = HAL_SFCG_INST();
|
||||
|
||||
if (enable == true) {
|
||||
inst_scfg->DEV_CTL3 |= NPCX_DEV_CTL3_I3C_MODE_BIT(module_id);
|
||||
} else {
|
||||
inst_scfg->DEV_CTL3 &= ~NPCX_DEV_CTL3_I3C_MODE_BIT(module_id);
|
||||
}
|
||||
#else
|
||||
LOG_ERR("%s: i3c target select not supported yet", __func__);
|
||||
#endif
|
||||
}
|
||||
|
||||
void npcx_dbg_freeze_enable(bool enable)
|
||||
{
|
||||
const uintptr_t dbg_base = npcx_scfg_cfg.base_dbg;
|
||||
|
|
|
|||
|
|
@ -85,6 +85,15 @@ bool npcx_lvol_get_detect_level(int lvol_ctrl, int lvol_bit);
|
|||
*/
|
||||
void npcx_host_interface_sel(enum npcx_hif_type hif_type);
|
||||
|
||||
/**
|
||||
* @brief Select the I3C module controller or target mode for the mdma
|
||||
* module operation.
|
||||
*
|
||||
* @param module i3c device
|
||||
* @param enable true to enable target mode, false to controller mode.
|
||||
*/
|
||||
void npcx_i3c_target_sel(uint8_t module, bool enable);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue