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mimxrt1050: fix dcdc value change process

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- to check status bit to make sure DCDC output is stable

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
This commit is contained in:
Ryan QIAN 2018-05-14 07:45:59 +08:00 • committed by Maureen Helm
commit 5757b4482e
1 changed files with 5 additions and 0 deletions
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5
arch/arm/soc/nxp_imx/rt/soc.c
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@ -58,6 +58,11 @@ static ALWAYS_INLINE void clkInit(void)
/* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz
*/ */
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
/* Waiting for DCDC_STS_DC_OK bit is asserted */
while (DCDC_REG0_STS_DC_OK_MASK !=
(DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) {
;
}
#ifdef CONFIG_INIT_ARM_PLL #ifdef CONFIG_INIT_ARM_PLL
CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */ CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */