diff --git a/dts/arm/cc3200_launchxl.fixup b/dts/arm/cc3200_launchxl.fixup index 6b50c357c39..76123bbeb26 100644 --- a/dts/arm/cc3200_launchxl.fixup +++ b/dts/arm/cc3200_launchxl.fixup @@ -1,4 +1,4 @@ -#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #define EXCEPTION_UARTA0 TI_CC32XX_UART_4000C000_IRQ_0 #define CONFIG_UART_CC32XX_IRQ_PRI TI_CC32XX_UART_4000C000_IRQ_0_PRIORITY diff --git a/dts/arm/cc32xx_launchxl.dtsi b/dts/arm/cc32xx_launchxl.dtsi index 01f9ce15c78..950f3131c14 100644 --- a/dts/arm/cc32xx_launchxl.dtsi +++ b/dts/arm/cc32xx_launchxl.dtsi @@ -45,5 +45,5 @@ }; &nvic { - num-irq-prio-bits = <3>; + arm,num-irq-priority-bits = <3>; }; diff --git a/dts/arm/frdm_k64f.fixup b/dts/arm/frdm_k64f.fixup index 352faf0bad0..9be8d392beb 100644 --- a/dts/arm/frdm_k64f.fixup +++ b/dts/arm/frdm_k64f.fixup @@ -1,4 +1,4 @@ -#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #define CONFIG_UART_MCUX_0_BAUD_RATE NXP_K64F_UART_4006A000_BAUD_RATE #define CONFIG_UART_MCUX_0_IRQ_PRI NXP_K64F_UART_4006A000_IRQ_0_PRIORITY diff --git a/dts/arm/frdm_kw41z.fixup b/dts/arm/frdm_kw41z.fixup index b216889afa1..489ff817876 100644 --- a/dts/arm/frdm_kw41z.fixup +++ b/dts/arm/frdm_kw41z.fixup @@ -1,4 +1,4 @@ -#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #define CONFIG_UART_MCUX_LPUART_0_BAUD_RATE NXP_KW41Z_LPUART_40054000_BAUD_RATE #define CONFIG_UART_MCUX_LPUART_0_IRQ_PRI NXP_KW41Z_LPUART_40054000_IRQ_0_PRIORITY diff --git a/dts/arm/hexiwear_k64.fixup b/dts/arm/hexiwear_k64.fixup index 352faf0bad0..9be8d392beb 100644 --- a/dts/arm/hexiwear_k64.fixup +++ b/dts/arm/hexiwear_k64.fixup @@ -1,4 +1,4 @@ -#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #define CONFIG_UART_MCUX_0_BAUD_RATE NXP_K64F_UART_4006A000_BAUD_RATE #define CONFIG_UART_MCUX_0_IRQ_PRI NXP_K64F_UART_4006A000_IRQ_0_PRIORITY diff --git a/dts/arm/nucleo_l476rg.fixup b/dts/arm/nucleo_l476rg.fixup index 18908745fd9..f90c1577e57 100644 --- a/dts/arm/nucleo_l476rg.fixup +++ b/dts/arm/nucleo_l476rg.fixup @@ -4,7 +4,7 @@ * generated data matches the driver definitions. */ -#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS #define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_BAUD_RATE diff --git a/dts/arm/nxp_k6x.dtsi b/dts/arm/nxp_k6x.dtsi index cc2d9e1f2f9..8bf600da6cd 100644 --- a/dts/arm/nxp_k6x.dtsi +++ b/dts/arm/nxp_k6x.dtsi @@ -271,5 +271,5 @@ }; &nvic { - num-irq-prio-bits = <4>; + arm,num-irq-priority-bits = <4>; }; diff --git a/dts/arm/nxp_kw41z.dtsi b/dts/arm/nxp_kw41z.dtsi index 2dee8e81ad1..cc166feb5db 100644 --- a/dts/arm/nxp_kw41z.dtsi +++ b/dts/arm/nxp_kw41z.dtsi @@ -182,5 +182,5 @@ }; &nvic { - num-irq-prio-bits = <2>; + arm,num-irq-priority-bits = <2>; }; diff --git a/dts/arm/olimexino_stm32.fixup b/dts/arm/olimexino_stm32.fixup index e004aeb117a..d1e7728e725 100644 --- a/dts/arm/olimexino_stm32.fixup +++ b/dts/arm/olimexino_stm32.fixup @@ -5,7 +5,7 @@ */ -#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS #define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_BAUD_RATE diff --git a/dts/arm/stm32f103xb.dtsi b/dts/arm/stm32f103xb.dtsi index 92b89f35ff8..003d7719f4d 100644 --- a/dts/arm/stm32f103xb.dtsi +++ b/dts/arm/stm32f103xb.dtsi @@ -93,5 +93,5 @@ }; &nvic { - num-irq-prio-bits = <4>; + arm,num-irq-priority-bits = <4>; }; diff --git a/dts/arm/stm32l476.dtsi b/dts/arm/stm32l476.dtsi index 579dc0ff052..107ae4364ff 100644 --- a/dts/arm/stm32l476.dtsi +++ b/dts/arm/stm32l476.dtsi @@ -125,5 +125,5 @@ }; &nvic { - num-irq-prio-bits = <4>; + arm,num-irq-priority-bits = <4>; }; diff --git a/dts/arm/v2m_beetle.dts b/dts/arm/v2m_beetle.dts index e90f2ac8d58..08916163364 100644 --- a/dts/arm/v2m_beetle.dts +++ b/dts/arm/v2m_beetle.dts @@ -47,5 +47,5 @@ }; &nvic { - num-irq-prio-bits = <3>; + arm,num-irq-priority-bits = <3>; }; diff --git a/dts/arm/v2m_beetle.fixup b/dts/arm/v2m_beetle.fixup index 1cf1b9e070b..1520ad9240c 100644 --- a/dts/arm/v2m_beetle.fixup +++ b/dts/arm/v2m_beetle.fixup @@ -1,4 +1,4 @@ -#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #define CMSDK_APB_UART_0_IRQ ARM_CMSDK_UART_40004000_IRQ_0 #define CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI ARM_CMSDK_UART_40004000_IRQ_0_PRIORITY diff --git a/dts/arm/yaml/arm,nvic.yaml b/dts/arm/yaml/arm,nvic.yaml index eaa68298609..4efbabefedc 100644 --- a/dts/arm/yaml/arm,nvic.yaml +++ b/dts/arm/yaml/arm,nvic.yaml @@ -18,7 +18,7 @@ properties: description: mmio register space generation: define - - num-irq-prio-bits: + - arm,num-irq-priority-bits: category: required type: int description: number of bits of IRQ priorities diff --git a/dts/arm/yaml/arm,v6m-nvic.yaml b/dts/arm/yaml/arm,v6m-nvic.yaml index b531b68af14..6ea13de79a8 100644 --- a/dts/arm/yaml/arm,v6m-nvic.yaml +++ b/dts/arm/yaml/arm,v6m-nvic.yaml @@ -18,7 +18,7 @@ properties: description: mmio register space generation: define - - num-irq-prio-bits: + - arm,num-irq-priority-bits: category: required type: int description: number of bits of IRQ priorities diff --git a/dts/arm/yaml/arm,v7m-nvic.yaml b/dts/arm/yaml/arm,v7m-nvic.yaml index 8f910fb92e7..0976b1b2dad 100644 --- a/dts/arm/yaml/arm,v7m-nvic.yaml +++ b/dts/arm/yaml/arm,v7m-nvic.yaml @@ -18,7 +18,7 @@ properties: description: mmio register space generation: define - - num-irq-prio-bits: + - arm,num-irq-priority-bits: category: required type: int description: number of bits of IRQ priorities