include: zephyr: Add the stm32u3 clock control and the reset register

Add the stm32u3 clock control and the RCC bus reset register offset

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
This commit is contained in:
Khaoula Bidani 2025-04-28 14:40:02 +02:00 committed by Daniel DeGrasse
commit 5673dc162f
3 changed files with 130 additions and 2 deletions

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@ -59,6 +59,8 @@
#include <zephyr/dt-bindings/clock/stm32n6_clock.h>
#elif defined(CONFIG_SOC_SERIES_STM32U0X)
#include <zephyr/dt-bindings/clock/stm32u0_clock.h>
#elif defined(CONFIG_SOC_SERIES_STM32U3X)
#include <zephyr/dt-bindings/clock/stm32u3_clock.h>
#elif defined(CONFIG_SOC_SERIES_STM32U5X)
#include <zephyr/dt-bindings/clock/stm32u5_clock.h>
#elif defined(CONFIG_SOC_SERIES_STM32WBAX)
@ -434,7 +436,8 @@
#define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode)
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay)
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u3_msi_clock, okay)
#define STM32_MSIS_ENABLED 1
#define STM32_MSIS_RANGE DT_PROP(DT_NODELABEL(clk_msis), msi_range)
#define STM32_MSIS_PLL_MODE DT_PROP(DT_NODELABEL(clk_msis), msi_pll_mode)
@ -444,7 +447,8 @@
#define STM32_MSIS_PLL_MODE 0
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u5_msi_clock, okay)
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u5_msi_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u3_msi_clock, okay)
#define STM32_MSIK_ENABLED 1
#define STM32_MSIK_RANGE DT_PROP(DT_NODELABEL(clk_msik), msi_range)
#define STM32_MSIK_PLL_MODE DT_PROP(DT_NODELABEL(clk_msik), msi_pll_mode)

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@ -0,0 +1,103 @@
/*
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U3_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U3_CLOCK_H_
#include "stm32_common_clocks.h"
/** Domain clocks */
/* RM0487, Figure 36 Clock tree for STM32U3 Series */
/** System clock */
/* defined in stm32_common_clocks.h */
/** Fixed clocks */
#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
#define STM32_SRC_HSI16 (STM32_SRC_HSE + 1)
#define STM32_SRC_HSI48 (STM32_SRC_HSI16 + 1)
#define STM32_SRC_MSIS (STM32_SRC_HSI48 + 1)
#define STM32_SRC_MSIK (STM32_SRC_MSIS + 1)
/** Bus clock */
#define STM32_SRC_HCLK (STM32_SRC_MSIK + 1)
#define STM32_SRC_PCLK1 (STM32_SRC_HCLK + 1)
#define STM32_SRC_PCLK2 (STM32_SRC_PCLK1 + 1)
#define STM32_SRC_PCLK3 (STM32_SRC_PCLK2 + 1)
/** Clock muxes */
/* #define STM32_SRC_ICLK TBD */
/** Bus clocks */
#define STM32_CLOCK_BUS_AHB1 0x088
#define STM32_CLOCK_BUS_AHB1_2 0x094
#define STM32_CLOCK_BUS_AHB2 0x08C
#define STM32_CLOCK_BUS_AHB2_2 0x090
#define STM32_CLOCK_BUS_APB1 0x09C
#define STM32_CLOCK_BUS_APB1_2 0x0A0
#define STM32_CLOCK_BUS_APB2 0x0A4
#define STM32_CLOCK_BUS_APB3 0x0A8
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
/** @brief RCC_CCIPRx register offset (RM0487.pdf) */
#define CCIPR1_REG 0x100
#define CCIPR2_REG 0x104
#define CCIPR3_REG 0x108
/** @brief RCC_BDCR register offset */
#define BDCR_REG 0x110
/** @brief RCC_CFGRx register offset */
#define CFGR1_REG 0x0C
/** @brief Device domain clocks selection helpers */
/** CCIPR1 devices */
#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR1_REG)
#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 2, CCIPR1_REG)
#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 4, CCIPR1_REG)
#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CCIPR1_REG)
#define I3C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 8, CCIPR1_REG)
#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 10, CCIPR1_REG)
#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 12, CCIPR1_REG)
#define I3C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 14, CCIPR1_REG)
#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 16, CCIPR1_REG)
#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR1_REG)
#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 20, CCIPR1_REG)
#define SYSTICK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR1_REG)
#define FDCAN1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR1_REG)
#define ICLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR1_REG)
#define USB1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 28, CCIPR1_REG)
#define TIMIC_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 29, CCIPR1_REG)
/** CCIPR2 devices */
#define ADF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)
#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 3, CCIPR2_REG)
#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 5, CCIPR2_REG)
#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 11, CCIPR2_REG)
#define ADCDAC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR2_REG)
#define DAC1SH_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 19, CCIPR2_REG)
#define OCTOSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 20, CCIPR2_REG)
/** CCIPR3 devices */
#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR3_REG)
#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CCIPR3_REG)
#define LPTIM34_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR3_REG)
#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR3_REG)
/** BDCR devices */
#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
/** CFGR1 devices */
#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG)
#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG)
/* MCO prescaler : division factor */
#define MCO_PRE_DIV_1 0
#define MCO_PRE_DIV_2 1
#define MCO_PRE_DIV_4 2
#define MCO_PRE_DIV_8 3
#define MCO_PRE_DIV_16 4
#define MCO_PRE_DIV_32 5
#define MCO_PRE_DIV_64 6
#define MCO_PRE_DIV_128 7
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U3_CLOCK_H_ */

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@ -0,0 +1,21 @@
/*
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32U3_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32U3_RESET_H_
#include "stm32-common.h"
/* RCC bus reset register offset */
#define STM32_RESET_BUS_AHB1 0x060
#define STM32_RESET_BUS_AHB2L 0x064
#define STM32_RESET_BUS_AHB2H 0x068
#define STM32_RESET_BUS_APB1L 0x074
#define STM32_RESET_BUS_APB1H 0x078
#define STM32_RESET_BUS_APB2 0x07C
#define STM32_RESET_BUS_APB3 0x080
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32U3_RESET_H_ */