include: zephyr: Add the stm32u3 clock control and the reset register
Add the stm32u3 clock control and the RCC bus reset register offset Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
This commit is contained in:
Khaoula Bidani
Daniel DeGrasse
parent
6e7b5bbdf1
commit
5673dc162f
3 changed files with 130 additions and 2 deletions
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@ -59,6 +59,8 @@
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#include <zephyr/dt-bindings/clock/stm32n6_clock.h>
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#elif defined(CONFIG_SOC_SERIES_STM32U0X)
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#include <zephyr/dt-bindings/clock/stm32u0_clock.h>
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#elif defined(CONFIG_SOC_SERIES_STM32U3X)
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#include <zephyr/dt-bindings/clock/stm32u3_clock.h>
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#elif defined(CONFIG_SOC_SERIES_STM32U5X)
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#include <zephyr/dt-bindings/clock/stm32u5_clock.h>
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#elif defined(CONFIG_SOC_SERIES_STM32WBAX)
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@ -434,7 +436,8 @@
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#define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode)
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#endif
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay)
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u3_msi_clock, okay)
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#define STM32_MSIS_ENABLED 1
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#define STM32_MSIS_RANGE DT_PROP(DT_NODELABEL(clk_msis), msi_range)
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#define STM32_MSIS_PLL_MODE DT_PROP(DT_NODELABEL(clk_msis), msi_pll_mode)
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@ -444,7 +447,8 @@
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#define STM32_MSIS_PLL_MODE 0
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#endif
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u5_msi_clock, okay)
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u5_msi_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u3_msi_clock, okay)
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#define STM32_MSIK_ENABLED 1
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#define STM32_MSIK_RANGE DT_PROP(DT_NODELABEL(clk_msik), msi_range)
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#define STM32_MSIK_PLL_MODE DT_PROP(DT_NODELABEL(clk_msik), msi_pll_mode)
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103
include/zephyr/dt-bindings/clock/stm32u3_clock.h
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103
include/zephyr/dt-bindings/clock/stm32u3_clock.h
Normal file
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@ -0,0 +1,103 @@
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/*
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* Copyright (c) 2025 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U3_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U3_CLOCK_H_
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#include "stm32_common_clocks.h"
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/** Domain clocks */
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/* RM0487, Figure 36 Clock tree for STM32U3 Series */
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/** System clock */
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/* defined in stm32_common_clocks.h */
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/** Fixed clocks */
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#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
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#define STM32_SRC_HSI16 (STM32_SRC_HSE + 1)
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#define STM32_SRC_HSI48 (STM32_SRC_HSI16 + 1)
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#define STM32_SRC_MSIS (STM32_SRC_HSI48 + 1)
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#define STM32_SRC_MSIK (STM32_SRC_MSIS + 1)
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/** Bus clock */
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#define STM32_SRC_HCLK (STM32_SRC_MSIK + 1)
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#define STM32_SRC_PCLK1 (STM32_SRC_HCLK + 1)
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#define STM32_SRC_PCLK2 (STM32_SRC_PCLK1 + 1)
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#define STM32_SRC_PCLK3 (STM32_SRC_PCLK2 + 1)
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/** Clock muxes */
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/* #define STM32_SRC_ICLK TBD */
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/** Bus clocks */
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#define STM32_CLOCK_BUS_AHB1 0x088
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#define STM32_CLOCK_BUS_AHB1_2 0x094
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#define STM32_CLOCK_BUS_AHB2 0x08C
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#define STM32_CLOCK_BUS_AHB2_2 0x090
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#define STM32_CLOCK_BUS_APB1 0x09C
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#define STM32_CLOCK_BUS_APB1_2 0x0A0
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#define STM32_CLOCK_BUS_APB2 0x0A4
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#define STM32_CLOCK_BUS_APB3 0x0A8
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#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
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#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
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/** @brief RCC_CCIPRx register offset (RM0487.pdf) */
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#define CCIPR1_REG 0x100
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#define CCIPR2_REG 0x104
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#define CCIPR3_REG 0x108
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/** @brief RCC_BDCR register offset */
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#define BDCR_REG 0x110
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/** @brief RCC_CFGRx register offset */
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#define CFGR1_REG 0x0C
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/** @brief Device domain clocks selection helpers */
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/** CCIPR1 devices */
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#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR1_REG)
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#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 2, CCIPR1_REG)
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#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 4, CCIPR1_REG)
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#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CCIPR1_REG)
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#define I3C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 8, CCIPR1_REG)
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#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 10, CCIPR1_REG)
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#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 12, CCIPR1_REG)
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#define I3C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 14, CCIPR1_REG)
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#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 16, CCIPR1_REG)
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#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR1_REG)
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#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 20, CCIPR1_REG)
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#define SYSTICK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR1_REG)
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#define FDCAN1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR1_REG)
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#define ICLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR1_REG)
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#define USB1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 28, CCIPR1_REG)
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#define TIMIC_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 29, CCIPR1_REG)
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/** CCIPR2 devices */
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#define ADF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)
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#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 3, CCIPR2_REG)
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#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 5, CCIPR2_REG)
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#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 11, CCIPR2_REG)
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#define ADCDAC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR2_REG)
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#define DAC1SH_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 19, CCIPR2_REG)
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#define OCTOSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 20, CCIPR2_REG)
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/** CCIPR3 devices */
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#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR3_REG)
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#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CCIPR3_REG)
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#define LPTIM34_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR3_REG)
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#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR3_REG)
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/** BDCR devices */
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#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
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/** CFGR1 devices */
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#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG)
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#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG)
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/* MCO prescaler : division factor */
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#define MCO_PRE_DIV_1 0
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#define MCO_PRE_DIV_2 1
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#define MCO_PRE_DIV_4 2
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#define MCO_PRE_DIV_8 3
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#define MCO_PRE_DIV_16 4
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#define MCO_PRE_DIV_32 5
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#define MCO_PRE_DIV_64 6
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#define MCO_PRE_DIV_128 7
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U3_CLOCK_H_ */
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21
include/zephyr/dt-bindings/reset/stm32u3_reset.h
Normal file
21
include/zephyr/dt-bindings/reset/stm32u3_reset.h
Normal file
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@ -0,0 +1,21 @@
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/*
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* Copyright (c) 2025 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32U3_RESET_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32U3_RESET_H_
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#include "stm32-common.h"
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/* RCC bus reset register offset */
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#define STM32_RESET_BUS_AHB1 0x060
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#define STM32_RESET_BUS_AHB2L 0x064
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#define STM32_RESET_BUS_AHB2H 0x068
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#define STM32_RESET_BUS_APB1L 0x074
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#define STM32_RESET_BUS_APB1H 0x078
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#define STM32_RESET_BUS_APB2 0x07C
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#define STM32_RESET_BUS_APB3 0x080
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32U3_RESET_H_ */
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