From 561f31bb5494dc40a7a49d7d9fb814dd1e2ea442 Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Wed, 6 Mar 2024 23:50:55 -0300 Subject: [PATCH] soc: espressif: esp32s3: update to hal_espressif v5.1 Modify and reorganize SoC to meet updated hal. Signed-off-by: Sylvio Alves Signed-off-by: Lucas Tamborrino --- .../espressif/esp32s3/esp32s3_common.dtsi | 16 + .../zephyr/dt-bindings/clock/esp32s3_clock.h | 6 +- soc/espressif/esp32s3/CMakeLists.txt | 71 +- soc/espressif/esp32s3/Kconfig | 110 +-- soc/espressif/esp32s3/Kconfig.defconfig | 12 - soc/espressif/esp32s3/Kconfig.mac | 47 + soc/espressif/esp32s3/Kconfig.rtc | 46 + soc/espressif/esp32s3/default.ld | 801 +++++++++++------- soc/espressif/esp32s3/esp32s3-mp.c | 4 +- soc/espressif/esp32s3/loader.c | 98 --- soc/espressif/esp32s3/mcuboot.ld | 65 +- soc/espressif/esp32s3/power.c | 46 + soc/espressif/esp32s3/poweroff.c | 15 + soc/espressif/esp32s3/soc.c | 164 +--- soc/espressif/esp32s3/soc.h | 11 +- soc/espressif/esp32s3/soc_appcpu.c | 90 +- soc/espressif/esp32s3/soc_cache.c | 46 +- 17 files changed, 804 insertions(+), 844 deletions(-) create mode 100644 soc/espressif/esp32s3/Kconfig.mac create mode 100644 soc/espressif/esp32s3/Kconfig.rtc delete mode 100644 soc/espressif/esp32s3/loader.c create mode 100644 soc/espressif/esp32s3/power.c create mode 100644 soc/espressif/esp32s3/poweroff.c diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi index a879187cbd4..b02d38410ad 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi @@ -32,6 +32,7 @@ device_type = "cpu"; compatible = "cdns,tensilica-xtensa-lx7"; reg = <0>; + cpu-power-states = <&light_sleep &deep_sleep>; }; cpu1: cpu@1 { @@ -40,6 +41,21 @@ reg = <1>; }; + power-states { + light_sleep: light_sleep { + compatible = "zephyr,power-state"; + power-state-name = "standby"; + min-residency-us = <200>; + exit-latency-us = <133>; + }; + + deep_sleep: deep_sleep { + compatible = "zephyr,power-state"; + power-state-name = "soft-off"; + min-residency-us = <2000>; + exit-latency-us = <382>; + }; + }; }; wifi: wifi { diff --git a/include/zephyr/dt-bindings/clock/esp32s3_clock.h b/include/zephyr/dt-bindings/clock/esp32s3_clock.h index 817aee45890..68980d0c8bf 100644 --- a/include/zephyr/dt-bindings/clock/esp32s3_clock.h +++ b/include/zephyr/dt-bindings/clock/esp32s3_clock.h @@ -21,10 +21,8 @@ #define ESP32_CLK_CPU_240M 240000000 /* Supported XTAL Frequencies */ -#define ESP32_CLK_XTAL_24M 0U -#define ESP32_CLK_XTAL_26M 1U -#define ESP32_CLK_XTAL_40M 2U -#define ESP32_CLK_XTAL_AUTO 3U +#define ESP32_CLK_XTAL_32M 32 +#define ESP32_CLK_XTAL_40M 40 /* Supported RTC fast clock frequencies */ #define ESP32_RTC_FAST_CLK_FREQ_8M 8500000U diff --git a/soc/espressif/esp32s3/CMakeLists.txt b/soc/espressif/esp32s3/CMakeLists.txt index 75b9f0a3d7e..0a261dbe1e0 100644 --- a/soc/espressif/esp32s3/CMakeLists.txt +++ b/soc/espressif/esp32s3/CMakeLists.txt @@ -1,13 +1,13 @@ # SPDX-License-Identifier: Apache-2.0 -if(CONFIG_SOC_ESP32S3_APPCPU) +if (CONFIG_SOC_ESP32S3_APPCPU) zephyr_sources(soc_appcpu.c) else() zephyr_sources( soc.c soc_cache.c - loader.c esp32s3-mp.c + ../common/loader.c ) endif() @@ -15,65 +15,39 @@ zephyr_include_directories(.) zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c) +# Power Management +zephyr_library_sources_ifdef(CONFIG_PM power.c) +zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) + # get flash size to use in esptool as string math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") if(CONFIG_BOOTLOADER_ESP_IDF) - include(ExternalProject) - ## we use hello-world project, but I think any can be used. - set(espidf_components_dir ${ESP_IDF_PATH}/components) - set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) - set(espidf_build_dir ${espidf_prefix}/build) + set(bootloader_dir "${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}/zephyr/blobs/lib/${CONFIG_SOC_SERIES}") - ExternalProject_Add( - EspIdfBootloader - PREFIX ${espidf_prefix} - SOURCE_DIR ${espidf_components_dir}/bootloader/subproject - BINARY_DIR ${espidf_build_dir}/bootloader - CONFIGURE_COMMAND - ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} - -S ${espidf_components_dir}/bootloader/subproject - -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig - -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} - -DPYTHON_DEPS_CHECKED=1 - -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} - -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} - -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} - -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} - -DPYTHON=${PYTHON_EXECUTABLE} - BUILD_COMMAND - ${CMAKE_COMMAND} --build . - INSTALL_COMMAND "" # This particular build system has no install command - ) + if(EXISTS "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin") + file(COPY "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) + file(RENAME "${CMAKE_BINARY_DIR}/bootloader-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/bootloader.bin") + endif() - ExternalProject_Add( - EspPartitionTable - SOURCE_DIR ${espidf_components_dir}/partition_table - BINARY_DIR ${espidf_build_dir} - CONFIGURE_COMMAND "" - BUILD_COMMAND - ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q - --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin - INSTALL_COMMAND "" - ) + if(EXISTS "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin") + file(COPY "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) + file(RENAME "${CMAKE_BINARY_DIR}/partition-table-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/partition-table.bin") + endif() + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/bootloader.bin") - set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) - - add_dependencies(app EspIdfBootloader EspPartitionTable) - - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") - - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") + board_finalize_runner_args(esp32 "--esp-flash-partition_table=${CMAKE_BINARY_DIR}/partition-table.bin") board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") endif() if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) + if(CONFIG_BUILD_OUTPUT_BIN) set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py + COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esptool_py/esptool.py ARGS --chip esp32s3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) @@ -82,10 +56,12 @@ if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) if(CONFIG_MCUBOOT) board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") endif() + endif() ## When building for APPCPU -if(CONFIG_SOC_ESP32S3_APPCPU) +if (CONFIG_SOC_ESP32S3_APPCPU) + if(CONFIG_BUILD_OUTPUT_BIN) set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esp_bin2c_array.py @@ -93,7 +69,9 @@ if(CONFIG_SOC_ESP32S3_APPCPU) -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.c -a "esp32s3_appcpu_fw_array") endif() + else() + set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) # get code-partition slot0 address @@ -107,6 +85,7 @@ else() board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") + endif() if(CONFIG_MCUBOOT) diff --git a/soc/espressif/esp32s3/Kconfig b/soc/espressif/esp32s3/Kconfig index 33489ad6dc9..9862a1db0a4 100644 --- a/soc/espressif/esp32s3/Kconfig +++ b/soc/espressif/esp32s3/Kconfig @@ -10,6 +10,8 @@ config SOC_SERIES_ESP32S3 select XIP if !MCUBOOT select HAS_ESPRESSIF_HAL select CPU_HAS_FPU + select HAS_PM + select HAS_POWEROFF if SOC_SERIES_ESP32S3 @@ -38,95 +40,6 @@ config SOC_ENABLE_APPCPU help This hidden configuration lets PROCPU core to map and start APPCPU whenever IPM is enabled. -choice ESP32S3_RTC_CLK_SRC - prompt "RTC clock source" - default ESP32S3_RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - - config ESP32S3_RTC_CLK_SRC_INT_RC - bool "Internal 150kHz RC oscillator" - config ESP32S3_RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - config ESP32S3_RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XP pin" - select ESP_SYSTEM_RTC_EXT_OSC - config ESP32S3_RTC_CLK_SRC_INT_8MD256 - bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" -endchoice - -config ESP32S3_RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if ESP32S3_RTC_CLK_SRC_EXT_CRYS || ESP32S3_RTC_CLK_SRC_EXT_OSC || ESP32S3_RTC_CLK_SRC_INT_8MD256 - default 1024 if ESP32S3_RTC_CLK_SRC_INT_RC - range 0 27000 if ESP32S3_RTC_CLK_SRC_EXT_CRYS || ESP32S3_RTC_CLK_SRC_EXT_OSC || ESP32S3_RTC_CLK_SRC_INT_8MD256 - range 0 32766 if ESP32S3_RTC_CLK_SRC_INT_RC - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. - -choice ESP32_UNIVERSAL_MAC_ADDRESSES - bool "Number of universally administered (by IEEE) MAC address" - default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - help - Configure the number of universally administered (by IEEE) MAC addresses. - During initialization, MAC addresses for each network interface are generated or - derived from a single base MAC address. If the number of universal MAC addresses is four, - all four interfaces (WiFi station, WiFi softap, Bluetooth and Ethernet) receive a universally - administered MAC address. These are generated sequentially by adding 0, 1, 2 and 3 (respectively) - to the final octet of the base MAC address. If the number of universal MAC addresses is two, - only two interfaces (WiFi station and Bluetooth) receive a universally administered MAC address. - These are generated sequentially by adding 0 and 1 (respectively) to the base MAC address. - The remaining two interfaces (WiFi softap and Ethernet) receive local MAC addresses. - These are derived from the universal WiFi station and Bluetooth MAC addresses, respectively. - When using the default (Espressif-assigned) base MAC address, either setting can be used. - When using a custom universal MAC address range, the correct setting will depend on the - allocation of MAC addresses in this range (either 2 or 4 per device.) - -config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO - bool "Two" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - select ESP_MAC_ADDR_UNIVERSE_BT - -config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - bool "Four" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - select ESP_MAC_ADDR_UNIVERSE_WIFI_AP - select ESP_MAC_ADDR_UNIVERSE_BT - select ESP_MAC_ADDR_UNIVERSE_ETH - -endchoice # ESP32_UNIVERSAL_MAC_ADDRESSES - -config ESP_MAC_ADDR_UNIVERSE_WIFI_AP - bool - -config ESP_MAC_ADDR_UNIVERSE_WIFI_STA - bool - -config ESP_MAC_ADDR_UNIVERSE_BT - bool - -config ESP_MAC_ADDR_UNIVERSE_ETH - bool - -config ESP32_UNIVERSAL_MAC_ADDRESSES - int - default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO - default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - config ESP32_PHY_MAX_WIFI_TX_POWER int "Max WiFi/BLE TX power (dBm)" range 10 20 @@ -281,23 +194,4 @@ config MAC_BB_PD endmenu # Cache config -menu "PSRAM Clock and CS IO for ESP32S3" - depends on ESP_SPIRAM - -config DEFAULT_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 30 - help - The PSRAM Clock IO can be any unused GPIO, please refer to your hardware design. - -config DEFAULT_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 26 - help - The PSRAM CS IO can be any unused GPIO, please refer to your hardware design. - -endmenu # PSRAM clock and cs IO for ESP32S3 - endif # SOC_SERIES_ESP32S3 diff --git a/soc/espressif/esp32s3/Kconfig.defconfig b/soc/espressif/esp32s3/Kconfig.defconfig index 07f719a0bcc..2d61a5cfa4b 100644 --- a/soc/espressif/esp32s3/Kconfig.defconfig +++ b/soc/espressif/esp32s3/Kconfig.defconfig @@ -3,18 +3,6 @@ if SOC_SERIES_ESP32S3 -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC - -config ESPTOOLPY_FLASHFREQ_80M - default y - config FLASH_SIZE default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0) diff --git a/soc/espressif/esp32s3/Kconfig.mac b/soc/espressif/esp32s3/Kconfig.mac new file mode 100644 index 00000000000..5d51e8773b2 --- /dev/null +++ b/soc/espressif/esp32s3/Kconfig.mac @@ -0,0 +1,47 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32S3 + +choice ESP32S3_UNIVERSAL_MAC_ADDRESSES + bool "Number of universally administered (by IEEE) MAC address" + default ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR + help + Configure the number of universally administered (by IEEE) MAC addresses. + During initialization, MAC addresses for each network interface are generated or derived from a + single base MAC address. + If the number of universal MAC addresses is four, all four interfaces (WiFi station, WiFi softap, + Bluetooth and Ethernet) receive a universally administered MAC address. These are generated + sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address. + If the number of universal MAC addresses is two, only two interfaces (WiFi station and Bluetooth) + receive a universally administered MAC address. These are generated sequentially by adding 0 + and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethernet) + receive local MAC addresses. These are derived from the universal WiFi station and Bluetooth MAC + addresses, respectively. + When using the default (Espressif-assigned) base MAC address, either setting can be used. When using + a custom universal MAC address range, the correct setting will depend on the allocation of MAC + addresses in this range (either 2 or 4 per device.)ll depend on the + allocation of MAC addresses in this range (either 1 or 2 per device). + +config ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO + bool "Two" + select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_BT + +config ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR + bool "Four" + select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_WIFI_AP + select ESP_MAC_ADDR_UNIVERSE_BT + select ESP_MAC_ADDR_UNIVERSE_ETH + +endchoice # ESP32S3_UNIVERSAL_MAC_ADDRESSES + +config ESP32S3_UNIVERSAL_MAC_ADDRESSES + int + default 2 if ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO + default 4 if ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR + +endif # SOC_SERIES_ESP32S3 diff --git a/soc/espressif/esp32s3/Kconfig.rtc b/soc/espressif/esp32s3/Kconfig.rtc new file mode 100644 index 00000000000..526d4b909c9 --- /dev/null +++ b/soc/espressif/esp32s3/Kconfig.rtc @@ -0,0 +1,46 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32S3 + +choice RTC_CLK_SRC + prompt "RTC clock source" + default RTC_CLK_SRC_INT_RC + help + Choose which clock is used as RTC clock source. + + config RTC_CLK_SRC_INT_RC + bool "Internal 136kHz RC oscillator" + config RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + config RTC_CLK_SRC_EXT_OSC + bool "External 32kHz oscillator at 32K_XP pin" + select ESP_SYSTEM_RTC_EXT_OSC + config RTC_CLK_SRC_INT_8MD256 + bool "Internal 17.5MHz oscillator, divided by 256" +endchoice + +config RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 + default 1024 if RTC_CLK_SRC_INT_RC + range 0 27000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 + range 0 32766 if RTC_CLK_SRC_INT_RC + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. + + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: + + - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. + +endif # SOC_SERIES_ESP32S3 diff --git a/soc/espressif/esp32s3/default.ld b/soc/espressif/esp32s3/default.ld index 7c8aff31767..3a9aa37794d 100644 --- a/soc/espressif/esp32s3/default.ld +++ b/soc/espressif/esp32s3/default.ld @@ -30,7 +30,6 @@ #define SRAM_IRAM_ORG (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) #define SRAM_IRAM_SIZE (I_D_SRAM_SIZE + ICACHE_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) -#define DCACHE_SIZE 0x10000 #define SRAM_DRAM_ORG (SRAM_DRAM_START) #define DRAM0_0_SEG_LEN I_D_SRAM_SIZE @@ -41,8 +40,6 @@ #define RAMABLE_REGION dram0_0_seg #define ROMABLE_REGION ROM -#define EXT_RAM_ORG (0x3E000000 - CONFIG_ESP_SPIRAM_SIZE) - #ifdef CONFIG_FLASH_SIZE #define FLASH_SIZE CONFIG_FLASH_SIZE #else @@ -52,9 +49,12 @@ #ifdef CONFIG_BOOTLOADER_ESP_IDF #define IROM_SEG_ORG 0x42000020 #define IROM_SEG_LEN FLASH_SIZE-0x20 +#define IROM_SEG_ALIGN 0x10 #else #define IROM_SEG_ORG 0x42000000 #define IROM_SEG_LEN FLASH_SIZE +/* MCUBoot requires MMU page size alignment */ +#define IROM_SEG_ALIGN 0x10000 #endif #ifdef CONFIG_SOC_ENABLE_APPCPU @@ -65,8 +65,6 @@ #define APPCPU_DRAM_SIZE 0x0 #endif -#define IROM_SEG_ALIGN 0x10000 - /* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA. * Executing directly from LMA is not possible. */ #undef GROUP_ROM_LINK_IN @@ -82,18 +80,18 @@ MEMORY irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN - /* DROM is the first segment placed in generated binary. - * MCUboot binary for ESP32 has image header of 0x20 bytes. + /* MCUboot binary for ESP32 has image header of 0x20 bytes. * Additional load header of 0x20 bytes are appended to the image. * Hence, an offset of 0x40 is added to DROM segment origin. */ drom0_0_seg(R): org = 0x3C000040, len = FLASH_SIZE - 0x40 + /** - * `extern_ram_seg` and `drom0_0_seg` share the same bus and the address region. - * so we allocate `extern_ram_seg` at the end of the address region. + * `ext_ram_seg` and `drom0_0_seg` share the same bus and the address region. + * A dummy section is used to avoid overlap. See `.ext_ram.dummy` in `sections.ld.in` */ #if defined(CONFIG_ESP_SPIRAM) - ext_ram_seg(RWX): org = EXT_RAM_ORG, len = CONFIG_ESP_SPIRAM_SIZE + ext_ram_seg(RWX): org = 0x3C000040, len = CONFIG_ESP_SPIRAM_SIZE - 0x40 #endif /* RTC fast memory (executable). Persists over deep sleep. @@ -113,6 +111,8 @@ MEMORY #endif } +_esp_mmu_block_size = (CONFIG_MMU_PAGE_SIZE); + /* Default entry point: */ ENTRY(CONFIG_KERNEL_ENTRY) @@ -155,112 +155,85 @@ SECTIONS #include - _image_drom_start = LOADADDR(_RODATA_SECTION_NAME); - _image_drom_size = LOADADDR(_RODATA_SECTION_END) + SIZEOF(_RODATA_SECTION_END) - _image_drom_start; - _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME); + /* RTC fast memory holds RTC wake stub code */ + .rtc.text : + { + . = ALIGN(4); + _rtc_fast_start = ABSOLUTE(.); + _rtc_text_start = ABSOLUTE(.); + *(.rtc.literal .rtc.text) + *(.rtc.entry.text) + _rtc_text_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) - /* NOTE: .rodata section should be the first section in the linker script and no - * other section should appear before .rodata section. This is the requirement - * to align ROM section to 64K page offset. - * Adding .rodata as first section helps to reduce size of generated binary by - * few kBs. + /* This section located in RTC FAST Memory area. + * It holds data marked with RTC_FAST_ATTR attribute. + * See the file "esp_attr.h" for more information. */ - SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(0x10)) + .rtc.force_fast : { - _rodata_reserved_start = ABSOLUTE(.); - _rodata_start = ABSOLUTE(.); - - *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ - *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */ - - __rodata_region_start = ABSOLUTE(.); . = ALIGN(4); - #include + _rtc_force_fast_start = ABSOLUTE(.); - . = ALIGN(4); - *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__serial.a:uart_esp32.*) .rodata) - *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__serial.a:uart_esp32.*) .rodata.*) + *(.rtc.force_fast .rtc.force_fast.*) + . = ALIGN(4) ; + _rtc_force_fast_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION) - *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); - *(.xt_except_table) - *(.gcc_except_table .gcc_except_table.*) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - . = (. + 3) & ~ 3; - __eh_frame = ABSOLUTE(.); - KEEP(*(.eh_frame)) - . = (. + 7) & ~ 3; - - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); - __rodata_region_end = ABSOLUTE(.); - /* Literals are also RO data. */ - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - . = ALIGN(4); - *(.rodata_wlog) - *(.rodata_wlog*) - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) - - #include - #include - #include - #include - #include - #include - #include - #include - #include - - /* Create an explicit section at the end of all the data that shall be mapped into drom. - * This is used to calculate the size of the _image_drom_size variable */ - SECTION_PROLOGUE(_RODATA_SECTION_END,,ALIGN(0x10)) + /* RTC data section holds data marked with + * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. + */ + .rtc.data : { - _rodata_reserved_end = ABSOLUTE(.); - . = ALIGN(16); - _image_rodata_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + _rtc_data_start = ABSOLUTE(.); + *(.rtc.data) + *(.rtc.rodata) + _rtc_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) -#if defined(CONFIG_ESP_SPIRAM) - /* This section holds .ext_ram.bss data, and will be put in PSRAM */ - .ext_ram.bss (NOLOAD) : + .rtc.bss (NOLOAD) : + { + _rtc_bss_start = ABSOLUTE(.); + + *(.rtc.data) + *(.rtc.rodata) + + _rtc_bss_end = ABSOLUTE(.); + } GROUP_LINK_IN(rtc_slow_seg) + + /* This section holds data that should not be initialized at power up + * and will be retained during deep sleep. + * User data marked with RTC_NOINIT_ATTR will be placed + * into this section. See the file "esp_attr.h" for more information. + */ + .rtc_noinit (NOLOAD): { - _ext_ram_data_start = ABSOLUTE(.); - _ext_ram_bss_start = ABSOLUTE(.); - *(.ext_ram.bss*) . = ALIGN(4); - _ext_ram_bss_end = ABSOLUTE(.); - } > ext_ram_seg + _rtc_noinit_start = ABSOLUTE(.); + *(.rtc_noinit .rtc_noinit.*) + . = ALIGN(4) ; + _rtc_noinit_end = ABSOLUTE(.); + } GROUP_LINK_IN(rtc_slow_seg) - .ext_ram_noinit (NOLOAD) : + /* This section located in RTC SLOW Memory area. + * It holds data marked with RTC_SLOW_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_slow : { -#if defined(CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM) - *libdrivers__wifi.a:(.noinit .noinit.*) - *libsubsys__net__l2__ethernet.a:(.noinit .noinit.*) - *libsubsys__net__lib__config.a:(.noinit .noinit.*) - *libsubsys__net__ip.a:(.noinit .noinit.*) - *libsubsys__net.a:(.noinit .noinit.*) -#endif - _spiram_heap_start = ABSOLUTE(.); - . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE; + . = ALIGN(4); + _rtc_force_slow_start = ABSOLUTE(.); + *(.rtc.force_slow .rtc.force_slow.*) + . = ALIGN(4) ; + _rtc_force_slow_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - _ext_ram_data_end = ABSOLUTE(.); - } > ext_ram_seg -#endif + /* Get size of rtc slow data based on rtc_data_location alias */ + _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); + _rtc_fast_length = (_rtc_force_fast_end - _rtc_fast_start); + + ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), "RTC_SLOW segment data does not fit.") + ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), "RTC_FAST segment data does not fit.") /* Send .iram0 code to iram */ .iram0.vectors : ALIGN(4) @@ -308,21 +281,14 @@ SECTIONS _iram_text_start = ABSOLUTE(.); *(.iram1 .iram1.*) *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) - *libesp32.a:panic.*(.literal .text .literal.* .text.*) - *librtc.a:(.literal .text .literal.* .text.*) *libarch__xtensa__core.a:(.literal .text .literal.* .text.*) *libkernel.a:(.literal .text .literal.* .text.*) - *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) - *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) - *libzephyr.a:spiram*.*(.literal .text .literal.* .text.*) - *libzephyr.a:spi_timing*.*(.literal .text .literal.* .text.*) - *libzephyr.a:spi_flash*.*(.literal .text .literal.* .text.*) + *libzephyr.a:cbprintf_packaged.*(.literal .text .literal.* .text.*) *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*) *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) - *libzephyr.a:systimer_hal.*(.literal .text .literal.* .text.*) *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) @@ -331,16 +297,107 @@ SECTIONS *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_minimal.*(.literal .literal.* .text .text.*) *libzephyr.a:loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_mmu_map.*(.literal .literal.* .text .text.*) + *libdrivers__interrupt_controller.a:(.literal .literal.* .text .text.*) *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) - *libc.a:*(.literal .text .literal.* .text.*) + *liblib__libc__picolibc.a:string.*(.literal .text .literal.* .text.*) *libphy.a:(.phyiram .phyiram.*) *libgcov.a:(.literal .text .literal.* .text.*) + /* [mapping:esp_psram] */ + *libzephyr.a:mmu_psram_flash.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_psram_impl_quad.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_psram_impl_octal.*(.literal .literal.* .text .text.*) + + /* [mapping:hal] */ + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:ledc_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:i2c_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:systimer_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal_gpspi.*(.literal .text .literal.* .text.*) + + /* [mapping:soc] */ + *libzephyr.a:lldesc.*(.literal .literal.* .text .text.*) + + /* [mapping:log] */ + *(.literal.esp_log_write .text.esp_log_write) + *(.literal.esp_log_timestamp .text.esp_log_timestamp) + *(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp) + *(.literal.esp_log_impl_lock .text.esp_log_impl_lock) + *(.literal.esp_log_impl_lock_timeout .text.esp_log_impl_lock_timeout) + *(.literal.esp_log_impl_unlock .text.esp_log_impl_unlock) + + /* [mapping:spi_flash] */ + *libzephyr.a:spi_flash_chip_boya.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_gd.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_generic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_issi.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_mxic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_mxic_opi.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_th.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_winbond.*(.literal .literal.* .text .text.*) + *libzephyr.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + *libzephyr.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_wrap.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hpm_enable.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_oct_flash_init*(.literal .literal.* .text .text.*) + + /* [mapping:esp_system] */ + *libzephyr.a:esp_err.*(.literal .literal.* .text .text.*) + *(.literal.esp_system_abort .text.esp_system_abort) + + /* [mapping:esp_hw_support] */ + *(.literal.esp_cpu_stall .text.esp_cpu_stall) + *(.literal.esp_cpu_unstall .text.esp_cpu_unstall) + *(.literal.esp_cpu_reset .text.esp_cpu_reset) + *(.literal.esp_cpu_wait_for_intr .text.esp_cpu_wait_for_intr) + *(.literal.esp_cpu_compare_and_set .text.esp_cpu_compare_and_set) + *(.literal.esp_gpio_reserve_pins .text.esp_gpio_reserve_pins) + *(.literal.esp_gpio_is_pin_reserved .text.esp_gpio_is_pin_reserved) + *(.literal.rtc_vddsdio_get_config .text.rtc_vddsdio_get_config) + *(.literal.rtc_vddsdio_set_config .text.rtc_vddsdio_set_config) + *libzephyr.a:esp_memory_utils.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_sleep.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) + *libzephyr.a:systimer.*(.literal .literal.* .text .text.*) + *libzephyr.a:mspi_timing_config.*(.literal .literal.* .text .text.*) + *libzephyr.a:mspi_timing_tuning.*(.literal .literal.* .text .text.*) + *(.literal.sar_periph_ctrl_power_enable .text.sar_periph_ctrl_power_enable) + + /* [mapping:soc_pm] */ + *(.literal.GPIO_HOLD_MASK .text.GPIO_HOLD_MASK) + + /* [mapping:esp_rom] */ + *libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_cache_writeback_esp32s3.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_spiflash.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_systimer.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_wdt.*(.literal .literal.* .text .text.*) + + /* [mapping:esp_mm] */ + *libzephyr.a:esp_cache.*(.literal .literal.* .text .text.*) + #if defined(CONFIG_ESP32_WIFI_IRAM_OPT) - *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) - *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) + *libnet80211.a:(.wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) + *libpp.a:(.wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) + *libcoexist.a:(.wifi_slp_iram .wifi_slp_iram.*) + + /* [mapping:esp_wifi] */ + *(.literal.wifi_clock_enable_wrapper .text.wifi_clock_enable_wrapper) + *(.literal.wifi_clock_disable_wrapper .text.wifi_clock_disable_wrapper) + + /* [mapping:esp_phy] */ + *(.literal.esp_phy_enable .text.esp_phy_enable) + *(.literal.esp_phy_disable .text.esp_phy_disable) + *(.literal.esp_wifi_bt_power_domain_off .text.esp_wifi_bt_power_domain_off) #endif #if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) @@ -352,49 +409,190 @@ SECTIONS } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - /* Marks the end of IRAM code segment */ - .iram0.text_end (NOLOAD) : - { - /* ESP32-S3 memprot requires 16B padding for possible CPU - * prefetch and 256B alignment for PMS split lines */ - . = ALIGN(16); - _iram_text_end = ABSOLUTE(.); - } GROUP_LINK_IN(IRAM_REGION) - - .iram0.data : - { - . = ALIGN(16); - *(.iram.data) - *(.iram.data*) - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - - .iram0.bss (NOLOAD) : - { - . = ALIGN(16); - *(.iram.bss) - *(.iram.bss*) - - . = ALIGN(16); - _iram_end = ABSOLUTE(.); - } GROUP_LINK_IN(IRAM_REGION) - - - /* This section is required to skip .iram0.text area because iram0_0_seg and + /** + * This section is required to skip .iram0.text area because iram0_0_seg and * dram0_0_seg reflect the same address space on different buses. */ .dram0.dummy (NOLOAD): { - . = ALIGN (8); . = ORIGIN(dram0_0_seg) + MAX(_iram_end, SRAM_DIRAM_I_START) - SRAM_DIRAM_I_START; } GROUP_LINK_IN(RAMABLE_REGION) - /* Shared RAM */ - SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) + .dram0.data : + { + . = ALIGN (8); + __data_start = ABSOLUTE(.); + _image_ram_start = ABSOLUTE(.); + /* bluetooth library requires this symbol to be defined */ + _btdm_data_start = ABSOLUTE(.); + *libbtdm_app.a:(.data .data.*) + . = ALIGN (4); + _btdm_data_end = ABSOLUTE(.); + + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.srodata) + *(.srodata.*) + /* rodata for panic handler(libarch__xtensa__core.a) and all + * dependent functions should be placed in DRAM to avoid issue + * when flash cache is disabled */ + *libarch__xtensa__core.a:(.rodata .rodata.*) + *libkernel.a:fatal.*(.rodata .rodata.*) + *libkernel.a:init.*(.rodata .rodata.*) + *libzephyr.a:cbprintf_complete.*(.rodata .rodata.*) + *libzephyr.a:log_core.*(.rodata .rodata.*) + *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) + *libzephyr.a:log_output.*(.rodata .rodata.*) + *libzephyr.a:log_minimal.*(.rodata .rodata.*) + *libzephyr.a:loader.*(.rodata .rodata.*) + *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) + *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) + *libzephyr.a:esp_mmu_map.*(.rodata .rodata.*) + *libdrivers__interrupt_controller.a:(.rodata .rodata.*) + + /* [mapping:esp_psram] */ + *libzephyr.a:mmu_psram_flash.*(.rodata .rodata.*) + *libzephyr.a:esp_psram_impl_octal.*(.rodata .rodata.*) + *libzephyr.a:esp_psram_impl_quad.*(.rodata .rodata.*) + + /* [mapping:hal] */ + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:cache_hal.*(.rodata .rodata.*) + *libzephyr.a:ledc_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:i2c_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:wdt_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:systimer_hal.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_hal_gpspi.*(.rodata .rodata.*) + + /* [mapping:soc] */ + *libzephyr.a:lldesc.*(.rodata .rodata.*) + + /* [mapping:log] */ + *(.rodata.esp_log_write) + *(.rodata.esp_log_timestamp) + *(.rodata.esp_log_early_timestamp) + *(.rodata.esp_log_impl_lock) + *(.rodata.esp_log_impl_lock_timeout) + *(.rodata.esp_log_impl_unlock) + + /* [mapping:spi_flash] */ + *libzephyr.a:spi_flash_chip_boya.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_gd.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_generic.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_issi.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_mxic.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_mxic_opi.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_th.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_winbond.*(.rodata .rodata.*) + *libzephyr.a:memspi_host_driver.*(.rodata .rodata.*) + *libzephyr.a:flash_brownout_hook.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_wrap.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_hpm_enable.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_oct_flash_init.*(.rodata .rodata.*) + + /* [mapping:esp_mm] */ + *libzephyr.a:esp_cache.*(.rodata .rodata.*) + + /* [mapping:esp_hw_support] */ + *(.rodata.esp_cpu_stall) + *(.rodata.esp_cpu_unstall) + *(.rodata.esp_cpu_reset) + *(.rodata.esp_cpu_wait_for_intr) + *(.rodata.esp_cpu_compare_and_set) + *(.rodata.esp_gpio_reserve_pins) + *(.rodata.esp_gpio_is_pin_reserved) + *(.rodata.rtc_vddsdio_get_config) + *(.rodata.rtc_vddsdio_set_config) + *libzephyr.a:esp_memory_utils.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.*) + *libzephyr.a:systimer.*(.rodata .rodata.*) + *libzephyr.a:mspi_timing_config.*(.rodata .rodata.*) + *libzephyr.a:mspi_timing_tuning.*(.rodata .rodata.*) + *(.rodata.sar_periph_ctrl_power_enable) + + /* [mapping:soc_pm] */ + *(.rodata.GPIO_HOLD_MASK) + + /* [mapping:esp_rom] */ + *libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.rodata .rodata.*) + *libzephyr.a:esp_rom_cache_writeback_esp32s3.*(.rodata .rodata.*) + *libzephyr.a:esp_rom_spiflash.*(.rodata .rodata.*) + *libzephyr.a:esp_rom_systimer.*(.rodata .rodata.*) + *libzephyr.a:esp_rom_wdt.*(.rodata .rodata.*) + + /* [mapping:esp_system] */ + *libzephyr.a:esp_err.*(.rodata .rodata.*) + *(.rodata.esp_system_abort) + +#if defined(CONFIG_ESP32_WIFI_IRAM_OPT) + /* [mapping:esp_wifi] */ + *(.rodata.wifi_clock_enable_wrapper) + *(.rodata.wifi_clock_disable_wrapper) + + /* [mapping:esp_phy] */ + *(.rodata.esp_phy_enable) + *(.rodata.esp_phy_disable) + *(.rodata.esp_wifi_bt_power_domain_off) +#endif + + KEEP(*(.jcr)) + *(.dram1 .dram1.*) + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + #include + #include + #include + #include + #include + #include + + /* logging sections should be placed in RAM area to avoid flash cache disabled issues */ + #pragma push_macro("GROUP_ROM_LINK_IN") + #undef GROUP_ROM_LINK_IN + #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN + #include + #pragma pop_macro("GROUP_ROM_LINK_IN") + + .dram0.end : + { + . = ALIGN(4); + #include + . = ALIGN(4); + __data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + .noinit (NOLOAD): + { + . = ALIGN(4); + *(.noinit) + *(.noinit.*) + . = ALIGN(4) ; + } GROUP_LINK_IN(RAMABLE_REGION) + + /* Shared RAM */ + .dram0.bss (NOLOAD) : { . = ALIGN (8); _bss_start = ABSOLUTE(.); /* required by bluetooth library */ __bss_start = ABSOLUTE(.); + /* bluetooth library requires this symbol to be defined */ + _btdm_bss_start = ABSOLUTE(.); + *libbtdm_app.a:(.bss .bss.* COMMON) + . = ALIGN (4); + _btdm_bss_end = ABSOLUTE(.); + *(.dynsbss) *(.sbss) *(.sbss.*) @@ -413,93 +611,24 @@ SECTIONS __bss_end = ABSOLUTE(.); } GROUP_LINK_IN(RAMABLE_REGION) +#include + ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") - SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) - { - . = ALIGN(8); - *(.noinit) - *(.noinit.*) - . = ALIGN(8) ; - } GROUP_LINK_IN(RAMABLE_REGION) - - .dram0.data : - { - . = ALIGN (8); - __data_start = ABSOLUTE(.); - - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - /* rodata for panic handler(libarch__xtensa__core.a) and all - * dependent functions should be placed in DRAM to avoid issue - * when flash cache is disabled */ - *libarch__xtensa__core.a:(.rodata .rodata.*) - *libkernel.a:fatal.*(.rodata .rodata.*) - *libkernel.a:init.*(.rodata .rodata.*) - *libzephyr.a:cbprintf_complete*(.rodata .rodata.*) - *libzephyr.a:systimer_hal.*(.rodata .rodata.*) - *libzephyr.a:log_core.*(.rodata .rodata.*) - *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) - *libzephyr.a:log_output.*(.rodata .rodata.*) - *libzephyr.a:loader.*(.rodata .rodata.*) - *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) - *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) - - KEEP(*(.jcr)) - *(.dram1 .dram1.*) - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - - #include - #include - #include - #include - #include - - /* logging sections should be placed in RAM area to avoid flash cache disabled issues */ - #pragma push_macro("GROUP_ROM_LINK_IN") - #undef GROUP_ROM_LINK_IN - #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN - #include - #pragma pop_macro("GROUP_ROM_LINK_IN") - - .dram0.end : - { - . = ALIGN(4); - - #include - - . = ALIGN(4); - _end = ABSOLUTE(.); - __data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - _image_irom_start = LOADADDR(.flash.text); _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start; _image_irom_vaddr = ADDR(.flash.text); - .flash_text_dummy (NOLOAD): ALIGN(IROM_SEG_ALIGN) - { - . = SIZEOF(_RODATA_SECTION_NAME); - . = ALIGN(IROM_SEG_ALIGN) + 0x20; - } GROUP_LINK_IN(FLASH_CODE_REGION) - .flash.text : ALIGN(IROM_SEG_ALIGN) { _stext = .; + _instruction_reserved_start = ABSOLUTE(.); _text_start = ABSOLUTE(.); #if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) + #endif #if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) @@ -522,6 +651,7 @@ SECTIONS . += 16; _text_end = ABSOLUTE(.); + _instruction_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */ _etext = .; /* Similar to _iram_start, this symbol goes here so it is @@ -531,114 +661,154 @@ SECTIONS _flash_cache_start = ABSOLUTE(0); } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) - /* RTC fast memory holds RTC wake stub code, - * including from any source file named rtc_wake_stub*.c + /** + * This dummy section represents the .flash.text section but in default_rodata_seg. + * Thus, it must have its alignment and (at least) its size. */ - .rtc.text : + .flash_rodata_dummy (NOLOAD): + { + _flash_rodata_dummy_start = ABSOLUTE(.); + /* Start at the same alignment constraint than .flash.text */ + . = ALIGN(ALIGNOF(.flash.text)); + /* Create an empty gap as big as .flash.text section */ + . = . + SIZEOF(.flash.text); + /* Prepare the alignment of the section above. Few bytes (0x20) must be + * added for the mapping header. */ + . = ALIGN(_esp_mmu_block_size) + 0x40; + } GROUP_LINK_IN(RODATA_REGION) + + _image_drom_start = LOADADDR(.flash.rodata); + _image_drom_size = LOADADDR(.flash.rodata_end) + SIZEOF(.flash.rodata_end) - _image_drom_start; + _image_drom_vaddr = ADDR(.flash.rodata); + + .flash.rodata : ALIGN(IROM_SEG_ALIGN) + { + _flash_rodata_start = ABSOLUTE(.); + _rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ + _rodata_start = ABSOLUTE(.); + __rodata_region_start = ABSOLUTE(.); + . = ALIGN(4); + #include + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata) + *(.rodata.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + . = ALIGN(4); + __rodata_region_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + *(.rodata_wlog) + *(.rodata_wlog*) + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + #include + #include + #include + #include + #include + #include + #include + #include + #include + + /* Create an explicit section at the end of all the data that shall be mapped into drom. + * This is used to calculate the size of the _image_drom_size variable */ + .flash.rodata_end : ALIGN(0x10) { . = ALIGN(4); - _rtc_text_start = ABSOLUTE(.); - *(.rtc.literal .rtc.text) - *(.rtc.entry.text) - *rtc_wake_stub*.*(.literal .text .literal.* .text.*) - _rtc_text_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) + _rodata_reserved_end = ABSOLUTE(.); + _image_rodata_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) - /* This section is required to skip rtc.text area because rtc_iram_seg and - * rtc_data_seg are reflect the same address space on different buses. + /** + * This section is required to skip flash rodata sections, because `ext_ram_seg` + * and `drom0_0_seg` are on the same bus */ - .rtc.dummy : +#if defined(CONFIG_ESP_SPIRAM) + + .ext_ram.dummy (NOLOAD): { - _rtc_dummy_start = ABSOLUTE(.); - _rtc_fast_start = ABSOLUTE(.); - . = SIZEOF(.rtc.text); - _rtc_dummy_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION) + . = ORIGIN(ext_ram_seg) + (_rodata_reserved_end - _flash_rodata_dummy_start); + . = ALIGN (0x10000); + } GROUP_LINK_IN(ext_ram_seg) - /* This section located in RTC FAST Memory area. - * It holds data marked with RTC_FAST_ATTR attribute. - * See the file "esp_attr.h" for more information. - */ - .rtc.force_fast : + /* This section holds .ext_ram.bss data, and will be put in PSRAM */ + .ext_ram.bss (NOLOAD) : + { + _ext_ram_bss_start = ABSOLUTE(.); + *(.ext_ram.bss*) + . = ALIGN(4); + + _spiram_heap_start = ABSOLUTE(.); + . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE - (_spiram_heap_start - _ext_ram_bss_start); + . = ALIGN(4); + + _ext_ram_bss_end = ABSOLUTE(.); + } GROUP_LINK_IN(ext_ram_seg) + +#endif /* CONFIG_ESP_SPIRAM */ + + /* Marks the end of IRAM code segment */ + .iram0.text_end (NOLOAD) : + { + /* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and 256B alignment for PMS split lines */ + . += 16; + _iram_text_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) + + .iram0.data : { . = ALIGN(4); - _rtc_force_fast_start = ABSOLUTE(.); + _iram_data_start = ABSOLUTE(.); + *(.iram.data) + *(.iram.data*) + _iram_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - *(.rtc.force_fast .rtc.force_fast.*) - . = ALIGN(4) ; - _rtc_force_fast_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION) - - /* RTC data section holds RTC wake stub - * data/rodata, including from any source file - * named rtc_wake_stub*.c and the data marked with - * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. - */ - .rtc.data : - { - _rtc_data_start = ABSOLUTE(.); - *(.rtc.data) - *(.rtc.rodata) - *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*) - _rtc_data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - - /* RTC bss, from any source file named rtc_wake_stub*.c */ - .rtc.bss (NOLOAD) : - { - _rtc_bss_start = ABSOLUTE(.); - *rtc_wake_stub*.*(.bss .bss.*) - *rtc_wake_stub*.*(COMMON) - - *(.rtc.data) - *(.rtc.rodata) - - _rtc_bss_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - - /* RTC bss, from any source file named rtc_wake_stub*.c */ - .rtc.bss (NOLOAD) : - { - _rtc_bss_start = ABSOLUTE(.); - *rtc_wake_stub*.*(.bss .bss.*) - *rtc_wake_stub*.*(COMMON) - - _rtc_bss_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - - /* This section holds data that should not be initialized at power up - * and will be retained during deep sleep. - * User data marked with RTC_NOINIT_ATTR will be placed - * into this section. See the file "esp_attr.h" for more information. - */ - .rtc_noinit (NOLOAD): + .iram0.bss (NOLOAD) : { . = ALIGN(4); - _rtc_noinit_start = ABSOLUTE(.); - *(.rtc_noinit .rtc_noinit.*) - . = ALIGN(4) ; - _rtc_noinit_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - - /* This section located in RTC SLOW Memory area. - * It holds data marked with RTC_SLOW_ATTR attribute. - * See the file "esp_attr.h" for more information. - */ - .rtc.force_slow : - { + _iram_bss_start = ABSOLUTE(.); + *(.iram.bss) + *(.iram.bss*) + _iram_bss_end = ABSOLUTE(.); . = ALIGN(4); - _rtc_force_slow_start = ABSOLUTE(.); - *(.rtc.force_slow .rtc.force_slow.*) - . = ALIGN(4) ; - _rtc_force_slow_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + _iram_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) - /* Get size of rtc slow data based on rtc_data_location alias */ - _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); - _rtc_fast_length = (_rtc_force_fast_end - _rtc_fast_start); - - ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), "RTC_SLOW segment data does not fit.") - ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), "RTC_FAST segment data does not fit.") + /* Marks the end of data, bss and possibly rodata */ + .dram0.heap_start (NOLOAD) : + { + . = ALIGN (8); + /* Lowest possible start address for the heap */ + _heap_start = ABSOLUTE(.); + } GROUP_LINK_IN(RAMABLE_REGION) #ifdef CONFIG_GEN_ISR_TABLES #include @@ -687,7 +857,10 @@ _heap_sentry = 0x3fceb910; ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), "IRAM0 segment data does not fit.") +ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), + "DRAM segment data does not fit.") + #if defined(CONFIG_ESP_SPIRAM) -ASSERT(((_ext_ram_data_end - _ext_ram_data_start) <= CONFIG_ESP_SPIRAM_SIZE), +ASSERT(((_ext_ram_bss_end - _ext_ram_bss_start) <= CONFIG_ESP_SPIRAM_SIZE), "External SPIRAM overflowed.") -#endif /* CONFIG_ESP_SPIRAM */ +#endif diff --git a/soc/espressif/esp32s3/esp32s3-mp.c b/soc/espressif/esp32s3/esp32s3-mp.c index 5f20b64c27a..ecd75aee27c 100644 --- a/soc/espressif/esp32s3/esp32s3-mp.c +++ b/soc/espressif/esp32s3/esp32s3-mp.c @@ -11,8 +11,6 @@ #include #include -#include -#include #include static struct k_spinlock loglock; @@ -28,7 +26,7 @@ void smp_log(const char *msg) void esp_appcpu_start(void *entry_point) { - soc_ll_unstall_core(1); + esp_cpu_unstall(1); if (!REG_GET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN)) { REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN); diff --git a/soc/espressif/esp32s3/loader.c b/soc/espressif/esp32s3/loader.c deleted file mode 100644 index ab6da243cd8..00000000000 --- a/soc/espressif/esp32s3/loader.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include - -#include -#include "esp32s3/dport_access.h" -#include "soc/cache_memory.h" -#include -#include "soc/extmem_reg.h" -#include - -#ifdef CONFIG_BOOTLOADER_MCUBOOT - -#define BOOT_LOG_INF(_fmt, ...) \ - ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__) - -#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used)) - -extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr; -extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr; - -void __start(void); - -static HDR_ATTR void (*_entry_point)(void) = &__start; - -static int map_rom_segments(void) -{ - int rc = 0; - size_t _partition_offset = FIXED_PARTITION_OFFSET(slot0_partition); - uint32_t _app_irom_start = _partition_offset + (uint32_t)&_image_irom_start; - uint32_t _app_irom_size = (uint32_t)&_image_irom_size; - uint32_t _app_irom_vaddr = (uint32_t)&_image_irom_vaddr; - - uint32_t _app_drom_start = _partition_offset + (uint32_t)&_image_drom_start; - uint32_t _app_drom_size = (uint32_t)&_image_drom_size; - uint32_t _app_drom_vaddr = (uint32_t)&_image_drom_vaddr; - - uint32_t autoload = Cache_Suspend_DCache(); - - Cache_Invalidate_DCache_All(); - - /* Clear the MMU entries that are already set up, - * so the new app only has the mappings it creates. - */ - for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++) { - FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL; - } - - uint32_t drom_page_count = bootloader_cache_pages_to_map(_app_drom_size, _app_drom_vaddr); - - rc |= esp_rom_Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, - _app_drom_vaddr & MMU_FLASH_MASK, - _app_drom_start & MMU_FLASH_MASK, - 64, drom_page_count, 0); - - uint32_t irom_page_count = bootloader_cache_pages_to_map(_app_irom_size, _app_irom_vaddr); - - rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, - _app_irom_vaddr & MMU_FLASH_MASK, - _app_irom_start & MMU_FLASH_MASK, - 64, irom_page_count, 0); - - REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE0_BUS); - REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE1_BUS); - - Cache_Resume_DCache(autoload); - - /* Show map segments continue using same log format as during MCUboot phase */ - BOOT_LOG_INF("DROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map", - _app_drom_start, _app_drom_vaddr, _app_drom_size, _app_drom_size); - BOOT_LOG_INF("IROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map\r\n", - _app_irom_start, _app_irom_vaddr, _app_irom_size, _app_irom_size); - esp_rom_uart_tx_wait_idle(0); - - return rc; -} -#endif /* CONFIG_BOOTLOADER_MCUBOOT */ - -void __start(void) -{ -#ifdef CONFIG_BOOTLOADER_MCUBOOT - int err = map_rom_segments(); - - if (err != 0) { - ets_printf("Failed to setup XIP, aborting\n"); - abort(); - } -#endif - __esp_platform_start(); -} diff --git a/soc/espressif/esp32s3/mcuboot.ld b/soc/espressif/esp32s3/mcuboot.ld index 3d1049506ca..b562192a625 100644 --- a/soc/espressif/esp32s3/mcuboot.ld +++ b/soc/espressif/esp32s3/mcuboot.ld @@ -34,11 +34,41 @@ #define IROM_SEG_ALIGN 16 +/** Simplified memory map for the bootloader. + * Make sure the bootloader can load into main memory without overwriting itself. + * + * ESP32-S3 ROM static data usage is as follows: + * - 0x3fcd7e00 - 0x3fce9704: Shared buffers, used in UART/USB/SPI download mode only + * - 0x3fce9710 - 0x3fceb710: PRO CPU stack, can be reclaimed as heap after RTOS startup + * - 0x3fceb710 - 0x3fced710: APP CPU stack, can be reclaimed as heap after RTOS startup + * - 0x3fced710 - 0x3fcf0000: ROM .bss and .data (not easily reclaimable) + * + * The 2nd stage bootloader can take space up to the end of ROM shared + * buffers area (0x3fce9704). For alignment purpose we shall use value (0x3fce9700). + */ +/* The offset between Dbus and Ibus. Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. */ +iram_dram_offset = 0x6f0000; + +bootloader_usable_dram_end = 0x3fce9700; + +bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */ +bootloader_dram_seg_len = 0x6600; +bootloader_iram_loader_seg_len = 0x3000; +bootloader_iram_seg_len = 0x9000; + +/* Start of the lower region is determined by region size and the end of the higher region */ +bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead; +/* bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len; */ +/* We move the dram start to 0x3FCA0000 */ +bootloader_dram_seg_start = 0x3FCA0000; +bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len + iram_dram_offset; +bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len; + MEMORY { - iram_seg(RWX) : org = 0x403B6000, len = 0x8000 - iram_loader_seg(RWX) : org = 0x403BE000, len = 0x2000 - dram_seg(RW) : org = 0x3FCD0000, len = 0x6000 + iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len + iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len + dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len #ifdef CONFIG_GEN_ISR_TABLES IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 @@ -92,11 +122,6 @@ SECTIONS *(.gnu.linkonce.lit4.*) _lit4_end = ABSOLUTE(.); . = ALIGN(4); - _thread_local_start = ABSOLUTE(.); - *(.tdata) - *(.tdata.*) - *(.tbss) - *(.tbss.*) *(.rodata_wlog) *(.rodata_wlog*) _thread_local_end = ABSOLUTE(.); @@ -104,7 +129,6 @@ SECTIONS . = ALIGN(4); } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) - #include #include #include #include @@ -114,11 +138,6 @@ SECTIONS { __data_start = ABSOLUTE(.); - _btdm_data_start = ABSOLUTE(.); - *libbtdm_app.a:(.data .data.*) - . = ALIGN (4); - _btdm_data_end = ABSOLUTE(.); - *(.data) *(.data.*) *(.gnu.linkonce.d.*) @@ -129,6 +148,9 @@ SECTIONS *(.sdata2) *(.sdata2.*) *(.gnu.linkonce.s2.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.*) + KEEP(*(.jcr)) *(.dram1 .dram1.*) . = ALIGN(4); @@ -200,7 +222,7 @@ SECTIONS . = ALIGN (16); _loader_text_start = ABSOLUTE(.); *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */ + *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */ *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*) *libzephyr.a:bootloader_flash_config_esp32s3.*(.literal .text .literal.* .text.*) *libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) @@ -233,6 +255,11 @@ SECTIONS *libzephyr.a:app_cpu_start.*(.literal .text .literal.* .text.*) *esp_mcuboot.*(.literal .text .literal.* .text.*) *esp_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) + *(.fini.literal) *(.fini) *(.gnu.version) @@ -259,14 +286,6 @@ SECTIONS _bss_start = ABSOLUTE(.); /* required by bluetooth library */ __bss_start = ABSOLUTE(.); - _btdm_bss_start = ABSOLUTE(.); - *libbtdm_app.a:(.bss .bss.* COMMON) - . = ALIGN (4); - _btdm_bss_end = ABSOLUTE(.); - - /* Buffer for system heap should be placed in dram_seg */ - *libkernel.a:mempool.*(.noinit.kheap_buf__system_heap .noinit.*.kheap_buf__system_heap) - *(.dynsbss) *(.sbss) *(.sbss.*) diff --git a/soc/espressif/esp32s3/power.c b/soc/espressif/esp32s3/power.c new file mode 100644 index 00000000000..f292774bc11 --- /dev/null +++ b/soc/espressif/esp32s3/power.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#include +LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL); + +static uint32_t intenable; + +/* Invoke Low Power/System Off specific Tasks */ +void pm_state_set(enum pm_state state, uint8_t substate_id) +{ + ARG_UNUSED(substate_id); + + switch (state) { + case PM_STATE_STANDBY: + intenable = XTENSA_RSR("INTENABLE"); + __asm__ volatile ("waiti 0"); + break; + default: + LOG_DBG("Unsupported power state %u", state); + break; + } +} + +/* Handle SOC specific activity after Low Power Mode Exit */ +void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) +{ + ARG_UNUSED(substate_id); + + switch (state) { + case PM_STATE_STANDBY: + z_xt_ints_on(intenable); + esp_light_sleep_start(); + break; + default: + LOG_DBG("Unsupported power state %u", state); + break; + } +} diff --git a/soc/espressif/esp32s3/poweroff.c b/soc/espressif/esp32s3/poweroff.c new file mode 100644 index 00000000000..d08d40dda97 --- /dev/null +++ b/soc/espressif/esp32s3/poweroff.c @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include + +void z_sys_poweroff(void) +{ + /* Forces RTC domain to be always on */ + esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON); + esp_deep_sleep_start(); +} diff --git a/soc/espressif/esp32s3/soc.c b/soc/espressif/esp32s3/soc.c index d41732db14e..54af1c4d20b 100644 --- a/soc/espressif/esp32s3/soc.c +++ b/soc/espressif/esp32s3/soc.c @@ -8,9 +8,20 @@ #include #include #include +#include #include #include #include +#include +#include +#include +#include +#include + +#if CONFIG_ESP_SPIRAM +#include +#include +#endif #include #include @@ -20,21 +31,19 @@ #include #include -#include "esp_private/system_internal.h" -#include "esp32s3/rom/cache.h" -#include "esp32s3/rom/rtc.h" -#include "soc/syscon_reg.h" -#include "hal/soc_ll.h" -#include "hal/wdt_hal.h" -#include "soc/cpu.h" -#include "soc/gpio_periph.h" -#include "esp_spi_flash.h" -#include "esp_err.h" -#include "esp_timer.h" -#include "esp_app_format.h" -#include "esp_clk_internal.h" - -#include "esp32s3/spiram.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #ifdef CONFIG_MCUBOOT #include "bootloader_init.h" @@ -49,7 +58,7 @@ extern int _ext_ram_bss_end; extern void z_cstart(void); extern void esp_reset_reason_init(void); -#if CONFIG_SOC_ENABLE_APPCPU +#ifdef CONFIG_SOC_ENABLE_APPCPU extern const unsigned char esp32s3_appcpu_fw_array[]; void IRAM_ATTR esp_start_appcpu(void) @@ -86,7 +95,7 @@ void IRAM_ATTR esp_start_appcpu(void) esp_appcpu_start((void *)entry_addr); } -#endif /* CONFIG_SOC_ENABLE_APPCPU */ +#endif /* CONFIG_SOC_ENABLE_APPCPU*/ #ifndef CONFIG_MCUBOOT /* @@ -148,32 +157,40 @@ void IRAM_ATTR __esp_platform_start(void) */ esp_config_data_cache_mode(); - /* Apply SoC patches */ - esp_errata(); + esp_mspi_pin_init(); + + spi_flash_init_chip_state(); + + mspi_timing_flash_tuning(); + + esp_mmu_map_init(); #if CONFIG_ESP_SPIRAM - esp_err_t err = esp_spiram_init(); + esp_err_t err = esp_psram_init(); if (err != ESP_OK) { printk("Failed to Initialize external RAM, aborting.\n"); abort(); } - esp_spiram_init_cache(); - if (esp_spiram_get_size() < CONFIG_ESP_SPIRAM_SIZE) { + if (esp_psram_get_size() < CONFIG_ESP_SPIRAM_SIZE) { printk("External RAM size is less than configured, aborting.\n"); abort(); } - if (!esp_spiram_test()) { - printk("External RAM failed memory test!\n"); - abort(); + if (esp_psram_is_initialized()) { + if (!esp_psram_extram_test()) { + printk("External RAM failed memory test!"); + abort(); + } } memset(&_ext_ram_bss_start, 0, (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start)); #endif /* CONFIG_ESP_SPIRAM */ + /* Apply SoC patches */ + esp_errata(); /* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check on startup sequence * related issues in application. Hence disable that as we are about to start @@ -223,100 +240,3 @@ void sys_arch_reboot(int type) { esp_restart_noos(); } - -void IRAM_ATTR esp_restart_noos(void) -{ - /* disable interrupts */ - z_xt_ints_off(0xFFFFFFFF); - - /* enable RTC watchdog for 1 second */ - wdt_hal_context_t wdt_ctx; - uint32_t timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL); - - wdt_hal_init(&wdt_ctx, WDT_RWDT, 0, false); - wdt_hal_write_protect_disable(&wdt_ctx); - wdt_hal_config_stage(&wdt_ctx, WDT_STAGE0, timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM); - wdt_hal_config_stage(&wdt_ctx, WDT_STAGE1, timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); - - /* enable flash boot mode so that flash booting after restart is protected by the RTC WDT */ - wdt_hal_set_flashboot_en(&wdt_ctx, true); - wdt_hal_write_protect_enable(&wdt_ctx); - - /* disable TG0/TG1 watchdogs */ - wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; - - wdt_hal_write_protect_disable(&wdt0_context); - wdt_hal_disable(&wdt0_context); - wdt_hal_write_protect_enable(&wdt0_context); - - wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1}; - - wdt_hal_write_protect_disable(&wdt1_context); - wdt_hal_disable(&wdt1_context); - wdt_hal_write_protect_enable(&wdt1_context); - - /* Flush any data left in UART FIFOs */ - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - esp_rom_uart_tx_wait_idle(2); - - /* Disable cache */ - Cache_Disable_ICache(); - Cache_Disable_DCache(); - - const uint32_t core_id = cpu_hal_get_core_id(); -#if CONFIG_SMP - const uint32_t other_core_id = (core_id == 0) ? 1 : 0; - - soc_ll_reset_core(other_core_id); - soc_ll_stall_core(other_core_id); -#endif - - /* 2nd stage bootloader reconfigures SPI flash signals. */ - /* Reset them to the defaults expected by ROM */ - WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - - /* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */ - SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, - SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | SYSTEM_BT_RST | - SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | SYSTEM_SDIO_HOST_RST | - SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | SYSTEM_RW_BTMAC_RST | - SYSTEM_RW_BTLP_RST | SYSTEM_BLE_REG_RST | SYSTEM_PWR_REG_RST); - REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0); - - /* Reset timer/spi/uart */ - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | - SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); - - /* Reset DMA */ - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); - - SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); - CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); - - rtc_clk_cpu_freq_set_xtal(); - - /* Reset CPUs */ - if (core_id == 0) { - /* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */ - soc_ll_reset_core(1); - soc_ll_reset_core(0); - } else { - /* Running on APP CPU: need to reset PRO CPU and unstall it, */ - /* then reset APP CPU */ - soc_ll_reset_core(0); - soc_ll_stall_core(0); - soc_ll_reset_core(1); - } - - while (true) { - ; - } -} diff --git a/soc/espressif/esp32s3/soc.h b/soc/espressif/esp32s3/soc.h index e45b10cac2f..2cb247ca489 100644 --- a/soc/espressif/esp32s3/soc.h +++ b/soc/espressif/esp32s3/soc.h @@ -11,12 +11,11 @@ #include #include #include -#include "esp32s3/rom/cache.h" +#include #include -#include "soc/extmem_reg.h" -#include "soc/cache_memory.h" -#include "hal/cpu_hal.h" -#include "hal/cpu_types.h" +#include +#include +#include #include #include @@ -24,7 +23,7 @@ #include #include -#include +#include void __esp_platform_start(void); diff --git a/soc/espressif/esp32s3/soc_appcpu.c b/soc/espressif/esp32s3/soc_appcpu.c index 583f0b8119a..410e015e744 100644 --- a/soc/espressif/esp32s3/soc_appcpu.c +++ b/soc/espressif/esp32s3/soc_appcpu.c @@ -23,11 +23,11 @@ #include #include #include -#include +#include #include -#include +#include #include -#include +#include "esp_cpu.h" #include #include #include @@ -37,7 +37,7 @@ extern void z_cstart(void); static void core_intr_matrix_clear(void) { - uint32_t core_id = cpu_hal_get_core_id(); + uint32_t core_id = esp_cpu_get_core_id(); for (int i = 0; i < ETS_MAX_INTR_SOURCE; i++) { intr_matrix_set(core_id, i, ETS_INVALID_INUM); @@ -88,85 +88,3 @@ void sys_arch_reboot(int type) { esp_restart_noos(); } - -void IRAM_ATTR esp_restart_noos(void) -{ - /* disable interrupts */ - z_xt_ints_off(0xFFFFFFFF); - - /* enable RTC watchdog for 1 second */ - wdt_hal_context_t wdt_ctx; - uint32_t timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL); - - wdt_hal_init(&wdt_ctx, WDT_RWDT, 0, false); - wdt_hal_write_protect_disable(&wdt_ctx); - wdt_hal_config_stage(&wdt_ctx, WDT_STAGE0, timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM); - wdt_hal_config_stage(&wdt_ctx, WDT_STAGE1, timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); - - /* enable flash boot mode so that flash booting after restart is protected by the RTC WDT */ - wdt_hal_set_flashboot_en(&wdt_ctx, true); - wdt_hal_write_protect_enable(&wdt_ctx); - - /* disable TG0/TG1 watchdogs */ - wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; - - wdt_hal_write_protect_disable(&wdt0_context); - wdt_hal_disable(&wdt0_context); - wdt_hal_write_protect_enable(&wdt0_context); - - wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1}; - - wdt_hal_write_protect_disable(&wdt1_context); - wdt_hal_disable(&wdt1_context); - wdt_hal_write_protect_enable(&wdt1_context); - - /* Flush any data left in UART FIFOs */ - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - esp_rom_uart_tx_wait_idle(2); - - /* Disable cache */ - Cache_Disable_ICache(); - Cache_Disable_DCache(); - - /* 2nd stage bootloader reconfigures SPI flash signals. */ - /* Reset them to the defaults expected by ROM */ - WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - - /* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */ - SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, - SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | SYSTEM_BT_RST | - SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | SYSTEM_SDIO_HOST_RST | - SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | SYSTEM_RW_BTMAC_RST | - SYSTEM_RW_BTLP_RST | SYSTEM_BLE_REG_RST | SYSTEM_PWR_REG_RST); - REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0); - - /* Reset timer/spi/uart */ - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | - SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); - - /* Reset DMA */ - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); - - SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); - CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); - - rtc_clk_cpu_freq_set_xtal(); - - /* Running on APP CPU: need to reset PRO CPU and unstall it, */ - /* then reset APP CPU */ - soc_ll_reset_core(0); - soc_ll_stall_core(0); - soc_ll_reset_core(1); - - while (true) { - ; - } -} diff --git a/soc/espressif/esp32s3/soc_cache.c b/soc/espressif/esp32s3/soc_cache.c index 6bb33e60c69..65330b2f939 100644 --- a/soc/espressif/esp32s3/soc_cache.c +++ b/soc/espressif/esp32s3/soc_cache.c @@ -7,52 +7,54 @@ #include "soc.h" #ifndef CONFIG_MCUBOOT +extern int _instruction_reserved_start; +extern int _instruction_reserved_end; extern int _rodata_reserved_start; extern int _rodata_reserved_end; + extern void rom_config_data_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, - uint8_t cfg_cache_line_size); + uint8_t cfg_cache_line_size); extern void rom_config_instruction_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, - uint8_t cfg_cache_line_size); -extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); + uint8_t cfg_cache_line_size); extern void Cache_Set_IDROM_MMU_Info(uint32_t instr_page_num, uint32_t rodata_page_num, - uint32_t rodata_start, uint32_t rodata_end, - int i_off, int ro_off); + uint32_t rodata_start, uint32_t rodata_end, int i_off, + int ro_off); extern void Cache_Enable_ICache(uint32_t autoload); void IRAM_ATTR esp_config_instruction_cache_mode(void) { rom_config_instruction_cache_mode(CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE, - CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS, - CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE); + CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS, + CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE); Cache_Suspend_DCache(); } void IRAM_ATTR esp_config_data_cache_mode(void) { - int s_instr_flash2spiram_off = 0; - int s_rodata_flash2spiram_off = 0; - rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE, - CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS, - CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE); + CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS, + CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE); Cache_Resume_DCache(0); /* Configure the Cache MMU size for instruction and rodata in flash. */ - uint32_t rodata_reserved_start_align = - (uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1); + uint32_t _instruction_size = + (uint32_t)&_instruction_reserved_end - (uint32_t)&_instruction_reserved_start; uint32_t cache_mmu_irom_size = - ((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * sizeof(uint32_t); + ((_instruction_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE) * + sizeof(uint32_t); + uint32_t _rodata_size = (uint32_t)&_rodata_reserved_end - (uint32_t)&_rodata_reserved_start; uint32_t cache_mmu_drom_size = - (((uint32_t)&_rodata_reserved_end - rodata_reserved_start_align + MMU_PAGE_SIZE - 1) - / MMU_PAGE_SIZE) * sizeof(uint32_t); + ((_rodata_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE) * + sizeof(uint32_t); + Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size); + int s_instr_flash2spiram_off = 0; + int s_rodata_flash2spiram_off = 0; Cache_Set_IDROM_MMU_Info(cache_mmu_irom_size / sizeof(uint32_t), - cache_mmu_drom_size / sizeof(uint32_t), - (uint32_t)&_rodata_reserved_start, - (uint32_t)&_rodata_reserved_end, - s_instr_flash2spiram_off, - s_rodata_flash2spiram_off); + cache_mmu_drom_size / sizeof(uint32_t), + (uint32_t)&_rodata_reserved_start, (uint32_t)&_rodata_reserved_end, + s_instr_flash2spiram_off, s_rodata_flash2spiram_off); } #endif /* CONFIG_MCUBOOT */