From 55caa7b7434e769c5da2680a5161da8ec7caa260 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Wed, 26 Sep 2018 15:31:53 -0500 Subject: [PATCH] drivers: spi: Select HAS_DTS_SPI in designware driver Makes the designware spi driver consistent with other spi drivers by selecting HAS_DTS_SPI in the driver. This required adding spi nodes and dts fixups to several arc and x86 socs, as well as enabling those nodes in associated boards. Also refactors the driver to use the base address, interrupt number, and interrupt priority from dts. Signed-off-by: Maureen Helm --- .../arc/arduino_101_sss/arduino_101_sss.dts | 8 +++ .../arc/em_starterkit/em_starterkit_em7d.dts | 8 +++ .../quark_se_c1000_ss_devboard.dts | 8 +++ boards/x86/arduino_101/arduino_101.dts | 12 ++++ .../x86/quark_d2000_crb/quark_d2000_crb.dts | 4 ++ .../quark_se_c1000_devboard.dts | 8 +++ drivers/spi/Kconfig.dw | 1 + drivers/spi/spi_dw.c | 72 +++++++++---------- dts/arc/quark_se_c1000_ss.dtsi | 24 +++++++ dts/x86/intel_curie.dtsi | 33 +++++++++ dts/x86/intel_quark_d2000.dtsi | 11 +++ soc/arc/quark_se_c1000_ss/Kconfig.defconfig | 6 -- soc/arc/quark_se_c1000_ss/dts.fixup | 18 +++++ soc/arc/snps_emsk/dts.fixup | 16 ++--- .../quark_d2000/Kconfig.defconfig.series | 2 - soc/x86/intel_quark/quark_d2000/dts.fixup | 5 ++ .../quark_se/Kconfig.defconfig.series | 9 --- soc/x86/intel_quark/quark_se/dts.fixup | 15 ++++ 18 files changed, 199 insertions(+), 61 deletions(-) diff --git a/boards/arc/arduino_101_sss/arduino_101_sss.dts b/boards/arc/arduino_101_sss/arduino_101_sss.dts index 520738a9198..afe21a8312f 100644 --- a/boards/arc/arduino_101_sss/arduino_101_sss.dts +++ b/boards/arc/arduino_101_sss/arduino_101_sss.dts @@ -50,3 +50,11 @@ &adc0 { status = "ok"; }; + +&spi0 { + status = "ok"; +}; + +&spi1 { + status = "ok"; +}; diff --git a/boards/arc/em_starterkit/em_starterkit_em7d.dts b/boards/arc/em_starterkit/em_starterkit_em7d.dts index 6a8a4faa0c9..5558583eafa 100644 --- a/boards/arc/em_starterkit/em_starterkit_em7d.dts +++ b/boards/arc/em_starterkit/em_starterkit_em7d.dts @@ -28,3 +28,11 @@ status = "ok"; current-speed = <115200>; }; + +&spi0 { + status = "ok"; +}; + +&spi1 { + status = "ok"; +}; diff --git a/boards/arc/quark_se_c1000_ss_devboard/quark_se_c1000_ss_devboard.dts b/boards/arc/quark_se_c1000_ss_devboard/quark_se_c1000_ss_devboard.dts index 566db5018ff..5bd1a4cc206 100644 --- a/boards/arc/quark_se_c1000_ss_devboard/quark_se_c1000_ss_devboard.dts +++ b/boards/arc/quark_se_c1000_ss_devboard/quark_se_c1000_ss_devboard.dts @@ -50,3 +50,11 @@ &adc0 { status = "ok"; }; + +&spi0 { + status = "ok"; +}; + +&spi1 { + status = "ok"; +}; diff --git a/boards/x86/arduino_101/arduino_101.dts b/boards/x86/arduino_101/arduino_101.dts index 1b9a0faaac6..591ad3e4e36 100644 --- a/boards/x86/arduino_101/arduino_101.dts +++ b/boards/x86/arduino_101/arduino_101.dts @@ -49,3 +49,15 @@ status = "ok"; clock-frequency = ; }; + +&spi0 { + status = "ok"; +}; + +&spi1 { + status = "ok"; +}; + +&spi2 { + status = "ok"; +}; diff --git a/boards/x86/quark_d2000_crb/quark_d2000_crb.dts b/boards/x86/quark_d2000_crb/quark_d2000_crb.dts index f9438a5dbcb..dd3c686f5c1 100644 --- a/boards/x86/quark_d2000_crb/quark_d2000_crb.dts +++ b/boards/x86/quark_d2000_crb/quark_d2000_crb.dts @@ -41,3 +41,7 @@ &adc0 { status = "ok"; }; + +&spi0 { + status = "ok"; +}; diff --git a/boards/x86/quark_se_c1000_devboard/quark_se_c1000_devboard.dts b/boards/x86/quark_se_c1000_devboard/quark_se_c1000_devboard.dts index fa77be649ac..13ed8a13c3f 100644 --- a/boards/x86/quark_se_c1000_devboard/quark_se_c1000_devboard.dts +++ b/boards/x86/quark_se_c1000_devboard/quark_se_c1000_devboard.dts @@ -49,3 +49,11 @@ status = "ok"; clock-frequency = ; }; + +&spi0 { + status = "ok"; +}; + +&spi1 { + status = "ok"; +}; diff --git a/drivers/spi/Kconfig.dw b/drivers/spi/Kconfig.dw index f777605d938..ce10f870bdf 100644 --- a/drivers/spi/Kconfig.dw +++ b/drivers/spi/Kconfig.dw @@ -8,6 +8,7 @@ menuconfig SPI_DW bool "Designware SPI controller driver" + select HAS_DTS_SPI help Enable support for Designware's SPI controllers. diff --git a/drivers/spi/spi_dw.c b/drivers/spi/spi_dw.c index eedf9407aa9..ca7d0305108 100644 --- a/drivers/spi/spi_dw.c +++ b/drivers/spi/spi_dw.c @@ -539,7 +539,7 @@ struct spi_dw_data spi_dw_data_port_0 = { }; const struct spi_dw_config spi_dw_config_0 = { - .regs = SPI_DW_PORT_0_REGS, + .regs = CONFIG_SPI_0_BASE_ADDRESS, #ifdef CONFIG_SPI_DW_PORT_0_CLOCK_GATE .clock_name = CONFIG_SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME, .clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_0_CLOCK_GATE_SUBSYS), @@ -556,21 +556,21 @@ DEVICE_AND_API_INIT(spi_dw_port_0, CONFIG_SPI_0_NAME, spi_dw_init, void spi_config_0_irq(void) { #ifdef CONFIG_SPI_DW_PORT_0_INTERRUPT_SINGLE_LINE - IRQ_CONNECT(SPI_DW_PORT_0_IRQ, CONFIG_SPI_0_IRQ_PRI, + IRQ_CONNECT(CONFIG_SPI_0_IRQ, CONFIG_SPI_0_IRQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_0), SPI_DW_IRQ_FLAGS); - irq_enable(SPI_DW_PORT_0_IRQ); + irq_enable(CONFIG_SPI_0_IRQ); _spi_int_unmask(SPI_DW_PORT_0_INT_MASK); #else - IRQ_CONNECT(IRQ_SPI0_RX_AVAIL, CONFIG_SPI_0_IRQ_PRI, + IRQ_CONNECT(CONFIG_SPI_0_IRQ_RX_AVAIL, CONFIG_SPI_0_IRQ_RX_AVAIL_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_0), SPI_DW_IRQ_FLAGS); - IRQ_CONNECT(IRQ_SPI0_TX_REQ, CONFIG_SPI_0_IRQ_PRI, + IRQ_CONNECT(CONFIG_SPI_0_IRQ_TX_REQ, CONFIG_SPI_0_IRQ_TX_REQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_0), SPI_DW_IRQ_FLAGS); - IRQ_CONNECT(IRQ_SPI0_ERR_INT, CONFIG_SPI_0_IRQ_PRI, + IRQ_CONNECT(CONFIG_SPI_0_IRQ_ERR_INT, CONFIG_SPI_0_IRQ_ERR_INT_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_0), SPI_DW_IRQ_FLAGS); - irq_enable(IRQ_SPI0_RX_AVAIL); - irq_enable(IRQ_SPI0_TX_REQ); - irq_enable(IRQ_SPI0_ERR_INT); + irq_enable(CONFIG_SPI_0_IRQ_RX_AVAIL); + irq_enable(CONFIG_SPI_0_IRQ_TX_REQ); + irq_enable(CONFIG_SPI_0_IRQ_ERR_INT); _spi_int_unmask(SPI_DW_PORT_0_RX_INT_MASK); _spi_int_unmask(SPI_DW_PORT_0_TX_INT_MASK); @@ -587,7 +587,7 @@ struct spi_dw_data spi_dw_data_port_1 = { }; static const struct spi_dw_config spi_dw_config_1 = { - .regs = SPI_DW_PORT_1_REGS, + .regs = CONFIG_SPI_1_BASE_ADDRESS, #ifdef CONFIG_SPI_DW_PORT_1_CLOCK_GATE .clock_name = CONFIG_SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME, .clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_1_CLOCK_GATE_SUBSYS), @@ -604,21 +604,21 @@ DEVICE_AND_API_INIT(spi_dw_port_1, CONFIG_SPI_1_NAME, spi_dw_init, void spi_config_1_irq(void) { #ifdef CONFIG_SPI_DW_PORT_1_INTERRUPT_SINGLE_LINE - IRQ_CONNECT(SPI_DW_PORT_1_IRQ, CONFIG_SPI_1_IRQ_PRI, + IRQ_CONNECT(CONFIG_SPI_1_IRQ, CONFIG_SPI_1_IRQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_1), SPI_DW_IRQ_FLAGS); - irq_enable(SPI_DW_PORT_1_IRQ); + irq_enable(CONFIG_SPI_1_IRQ); _spi_int_unmask(SPI_DW_PORT_1_INT_MASK); #else - IRQ_CONNECT(IRQ_SPI1_RX_AVAIL, CONFIG_SPI_1_IRQ_PRI, + IRQ_CONNECT(CONFIG_SPI_1_IRQ_RX_AVAIL, CONFIG_SPI_1_IRQ_RX_AVAIL_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_1), SPI_DW_IRQ_FLAGS); - IRQ_CONNECT(IRQ_SPI1_TX_REQ, CONFIG_SPI_1_IRQ_PRI, + IRQ_CONNECT(CONFIG_SPI_1_IRQ_TX_REQ, CONFIG_SPI_1_IRQ_TX_REQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_1), SPI_DW_IRQ_FLAGS); - IRQ_CONNECT(IRQ_SPI1_ERR_INT, CONFIG_SPI_1_IRQ_PRI, + IRQ_CONNECT(CONFIG_SPI_1_IRQ_ERR_INT, CONFIG_SPI_1_IRQ_ERR_INT_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_1), SPI_DW_IRQ_FLAGS); - irq_enable(IRQ_SPI1_RX_AVAIL); - irq_enable(IRQ_SPI1_TX_REQ); - irq_enable(IRQ_SPI1_ERR_INT); + irq_enable(CONFIG_SPI_1_IRQ_RX_AVAIL); + irq_enable(CONFIG_SPI_1_IRQ_TX_REQ); + irq_enable(CONFIG_SPI_1_IRQ_ERR_INT); _spi_int_unmask(SPI_DW_PORT_1_RX_INT_MASK); _spi_int_unmask(SPI_DW_PORT_1_TX_INT_MASK); @@ -635,7 +635,7 @@ struct spi_dw_data spi_dw_data_port_2 = { }; static const struct spi_dw_config spi_dw_config_2 = { - .regs = SPI_DW_PORT_2_REGS, + .regs = CONFIG_SPI_2_BASE_ADDRESS, #ifdef CONFIG_SPI_DW_PORT_2_CLOCK_GATE .clock_name = CONFIG_SPI_DW_PORT_2_CLOCK_GATE_DRV_NAME, .clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_2_CLOCK_GATE_SUBSYS), @@ -652,21 +652,21 @@ DEVICE_AND_API_INIT(spi_dw_port_2, CONFIG_SPI_2_NAME, spi_dw_init, void spi_config_2_irq(void) { #ifdef CONFIG_SPI_DW_PORT_2_INTERRUPT_SINGLE_LINE - IRQ_CONNECT(SPI_DW_PORT_2_IRQ, CONFIG_SPI_2_IRQ_PRI, + IRQ_CONNECT(CONFIG_SPI_2_IRQ, CONFIG_SPI_2_IRQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_2), SPI_DW_IRQ_FLAGS); - irq_enable(SPI_DW_PORT_2_IRQ); + irq_enable(CONFIG_SPI_2_IRQ); _spi_int_unmask(SPI_DW_PORT_2_INT_MASK); #else - IRQ_CONNECT(IRQ_SPI2_RX_AVAIL, CONFIG_SPI_2_IRQ_PRI, + IRQ_CONNECT(CONFIG_SPI_2_IRQ_RX_AVAIL, CONFIG_SPI_2_IRQ_RX_AVAIL_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_2), SPI_DW_IRQ_FLAGS); - IRQ_CONNECT(IRQ_SPI2_TX_REQ, CONFIG_SPI_2_IRQ_PRI, + IRQ_CONNECT(CONFIG_SPI_2_IRQ_TX_REQ, CONFIG_SPI_2_IRQ_TX_REQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_2), SPI_DW_IRQ_FLAGS); - IRQ_CONNECT(IRQ_SPI2_ERR_INT, CONFIG_SPI_2_IRQ_PRI, + IRQ_CONNECT(CONFIG_SPI_2_IRQ_ERR_INT, CONFIG_SPI_2_IRQ_ERR_INT_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_2), SPI_DW_IRQ_FLAGS); - irq_enable(IRQ_SPI2_RX_AVAIL); - irq_enable(IRQ_SPI2_TX_REQ); - irq_enable(IRQ_SPI2_ERR_INT); + irq_enable(CONFIG_SPI_2_IRQ_RX_AVAIL); + irq_enable(CONFIG_SPI_2_IRQ_TX_REQ); + irq_enable(CONFIG_SPI_2_IRQ_ERR_INT); _spi_int_unmask(SPI_DW_PORT_2_RX_INT_MASK); _spi_int_unmask(SPI_DW_PORT_2_TX_INT_MASK); @@ -683,7 +683,7 @@ struct spi_dw_data spi_dw_data_port_3 = { }; static const struct spi_dw_config spi_dw_config_3 = { - .regs = SPI_DW_PORT_3_REGS, + .regs = CONFIG_SPI_3_BASE_ADDRESS, #ifdef CONFIG_SPI_DW_PORT_3_CLOCK_GATE .clock_name = CONFIG_SPI_DW_PORT_3_CLOCK_GATE_DRV_NAME, .clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_3_CLOCK_GATE_SUBSYS), @@ -700,21 +700,21 @@ DEVICE_AND_API_INIT(spi_dw_port_3, CONFIG_SPI_3_NAME, spi_dw_init, void spi_config_3_irq(void) { #ifdef CONFIG_SPI_DW_PORT_3_INTERRUPT_SINGLE_LINE - IRQ_CONNECT(SPI_DW_PORT_3_IRQ, CONFIG_SPI_3_IRQ_PRI, + IRQ_CONNECT(CONFIG_SPI_3_IRQ, CONFIG_SPI_3_IRQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_3), SPI_DW_IRQ_FLAGS); - irq_enable(SPI_DW_PORT_3_IRQ); + irq_enable(CONFIG_SPI_3_IRQ); _spi_int_unmask(SPI_DW_PORT_3_INT_MASK); #else - IRQ_CONNECT(IRQ_SPI3_RX_AVAIL, CONFIG_SPI_3_IRQ_PRI, + IRQ_CONNECT(CONFIG_SPI_3_IRQ_RX_AVAIL, CONFIG_SPI_3_IRQ_RX_AVAIL_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_3), SPI_DW_IRQ_FLAGS); - IRQ_CONNECT(IRQ_SPI3_TX_REQ, CONFIG_SPI_3_IRQ_PRI, + IRQ_CONNECT(CONFIG_SPI_3_IRQ_TX_REQ, CONFIG_SPI_3_IRQ_TX_REQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_3), SPI_DW_IRQ_FLAGS); - IRQ_CONNECT(IRQ_SPI3_ERR_INT, CONFIG_SPI_3_IRQ_PRI, + IRQ_CONNECT(CONFIG_SPI_3_IRQ_ERR_INT, CONFIG_SPI_3_IRQ_ERR_INT_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_3), SPI_DW_IRQ_FLAGS); - irq_enable(IRQ_SPI3_RX_AVAIL); - irq_enable(IRQ_SPI3_TX_REQ); - irq_enable(IRQ_SPI3_ERR_INT); + irq_enable(CONFIG_SPI_3_IRQ_RX_AVAIL); + irq_enable(CONFIG_SPI_3_IRQ_TX_REQ); + irq_enable(CONFIG_SPI_3_IRQ_ERR_INT); _spi_int_unmask(SPI_DW_PORT_3_RX_INT_MASK); _spi_int_unmask(SPI_DW_PORT_3_TX_INT_MASK); diff --git a/dts/arc/quark_se_c1000_ss.dtsi b/dts/arc/quark_se_c1000_ss.dtsi index a562ce12d0b..ce84ff57c2b 100644 --- a/dts/arc/quark_se_c1000_ss.dtsi +++ b/dts/arc/quark_se_c1000_ss.dtsi @@ -176,6 +176,30 @@ status = "disabled"; }; + spi0: spi@80010000 { + compatible = "snps,designware-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80010000 0x400>; + interrupts = <30 2>, <31 2>, <32 2>; + interrupt-names = "err-int", "rx-avail", "tx-req"; + interrupt-parent = <&core_intc>; + label = "SPI_0"; + status = "disabled"; + }; + + spi1: spi@80010100 { + compatible = "snps,designware-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80010100 0x400>; + interrupts = <33 2>, <34 2>, <35 2>; + interrupt-names = "err-int", "rx-avail", "tx-req"; + interrupt-parent = <&core_intc>; + label = "SPI_1"; + status = "disabled"; + }; + adc0: adc@80015000 { compatible = "snps,dw-adc"; #address-cells = <1>; diff --git a/dts/x86/intel_curie.dtsi b/dts/x86/intel_curie.dtsi index 1ec4409736a..5b1fee90983 100644 --- a/dts/x86/intel_curie.dtsi +++ b/dts/x86/intel_curie.dtsi @@ -136,5 +136,38 @@ status = "disabled"; }; + + spi0: spi@b0001000 { + compatible = "snps,designware-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xb0001000 0x400>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 2>; + interrupt-parent = <&intc>; + label = "SPI_0"; + status = "disabled"; + }; + + spi1: spi@b0001400 { + compatible = "snps,designware-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xb0001400 0x400>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 2>; + interrupt-parent = <&intc>; + label = "SPI_1"; + status = "disabled"; + }; + + spi2: spi@b0001800 { + compatible = "snps,designware-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xb0001800 0x400>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 2>; + interrupt-parent = <&intc>; + label = "SPI_2"; + status = "disabled"; + }; }; }; diff --git a/dts/x86/intel_quark_d2000.dtsi b/dts/x86/intel_quark_d2000.dtsi index 48a43423217..48b860d967d 100644 --- a/dts/x86/intel_quark_d2000.dtsi +++ b/dts/x86/intel_quark_d2000.dtsi @@ -108,5 +108,16 @@ status = "disabled"; }; + + spi0: spi@b0001000 { + compatible = "snps,designware-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xb0001000 0x400>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc>; + label = "SPI_0"; + status = "disabled"; + }; }; }; diff --git a/soc/arc/quark_se_c1000_ss/Kconfig.defconfig b/soc/arc/quark_se_c1000_ss/Kconfig.defconfig index 21403cf2eba..39b402838a2 100644 --- a/soc/arc/quark_se_c1000_ss/Kconfig.defconfig +++ b/soc/arc/quark_se_c1000_ss/Kconfig.defconfig @@ -181,9 +181,6 @@ config SPI_DW_PORT_0_CLOCK_GATE_DRV_NAME config SPI_DW_PORT_0_CLOCK_GATE_SUBSYS default 3 -config SPI_0_IRQ_PRI - default 1 - config SPI_1 def_bool y @@ -199,9 +196,6 @@ config SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME config SPI_DW_PORT_1_CLOCK_GATE_SUBSYS default 4 -config SPI_1_IRQ_PRI - default 1 - endif # SPI_DW endif # SPI diff --git a/soc/arc/quark_se_c1000_ss/dts.fixup b/soc/arc/quark_se_c1000_ss/dts.fixup index 3c215e699b8..550d2452bd7 100644 --- a/soc/arc/quark_se_c1000_ss/dts.fixup +++ b/soc/arc/quark_se_c1000_ss/dts.fixup @@ -74,4 +74,22 @@ #define CONFIG_ADC_0_NAME SNPS_DW_ADC_80015000_LABEL #define CONFIG_ADC_0_BASE_ADDRESS SNPS_DW_ADC_80015000_BASE_ADDRESS +#define CONFIG_SPI_0_BASE_ADDRESS SNPS_DESIGNWARE_SPI_80010000_BASE_ADDRESS +#define CONFIG_SPI_0_NAME SNPS_DESIGNWARE_SPI_80010000_LABEL +#define CONFIG_SPI_0_IRQ_ERR_INT SNPS_DESIGNWARE_SPI_80010000_IRQ_ERR_INT +#define CONFIG_SPI_0_IRQ_ERR_INT_PRI SNPS_DESIGNWARE_SPI_80010000_IRQ_ERR_INT_PRIORITY +#define CONFIG_SPI_0_IRQ_RX_AVAIL SNPS_DESIGNWARE_SPI_80010000_IRQ_RX_AVAIL +#define CONFIG_SPI_0_IRQ_RX_AVAIL_PRI SNPS_DESIGNWARE_SPI_80010000_IRQ_RX_AVAIL_PRIORITY +#define CONFIG_SPI_0_IRQ_TX_REQ SNPS_DESIGNWARE_SPI_80010000_IRQ_TX_REQ +#define CONFIG_SPI_0_IRQ_TX_REQ_PRI SNPS_DESIGNWARE_SPI_80010000_IRQ_TX_REQ_PRIORITY + +#define CONFIG_SPI_1_BASE_ADDRESS SNPS_DESIGNWARE_SPI_80010100_BASE_ADDRESS +#define CONFIG_SPI_1_NAME SNPS_DESIGNWARE_SPI_80010100_LABEL +#define CONFIG_SPI_1_IRQ_ERR_INT SNPS_DESIGNWARE_SPI_80010100_IRQ_ERR_INT +#define CONFIG_SPI_1_IRQ_ERR_INT_PRI SNPS_DESIGNWARE_SPI_80010100_IRQ_ERR_INT_PRIORITY +#define CONFIG_SPI_1_IRQ_RX_AVAIL SNPS_DESIGNWARE_SPI_80010100_IRQ_RX_AVAIL +#define CONFIG_SPI_1_IRQ_RX_AVAIL_PRI SNPS_DESIGNWARE_SPI_80010100_IRQ_RX_AVAIL_PRIORITY +#define CONFIG_SPI_1_IRQ_TX_REQ SNPS_DESIGNWARE_SPI_80010100_IRQ_TX_REQ +#define CONFIG_SPI_1_IRQ_TX_REQ_PRI SNPS_DESIGNWARE_SPI_80010100_IRQ_TX_REQ_PRIORITY + /* End of SoC Level DTS fixup file */ diff --git a/soc/arc/snps_emsk/dts.fixup b/soc/arc/snps_emsk/dts.fixup index 54761629b2c..c7ee290a9ee 100644 --- a/soc/arc/snps_emsk/dts.fixup +++ b/soc/arc/snps_emsk/dts.fixup @@ -82,16 +82,16 @@ /* * SPI configuration */ -#define SPI_DW_PORT_0_REGS SNPS_DESIGNWARE_SPI_F0006000_BASE_ADDRESS -#define SPI_DW_PORT_0_IRQ SNPS_DESIGNWARE_SPI_F0006000_IRQ_0 -#define CONFIG_SPI_0_NAME SNPS_DESIGNWARE_SPI_F0006000_LABEL -#define CONFIG_SPI_0_IRQ_PRI SNPS_DESIGNWARE_SPI_F0006000_IRQ_0_PRIORITY +#define CONFIG_SPI_0_BASE_ADDRESS SNPS_DESIGNWARE_SPI_F0006000_BASE_ADDRESS +#define CONFIG_SPI_0_NAME SNPS_DESIGNWARE_SPI_F0006000_LABEL +#define CONFIG_SPI_0_IRQ SNPS_DESIGNWARE_SPI_F0006000_IRQ_0 +#define CONFIG_SPI_0_IRQ_PRI SNPS_DESIGNWARE_SPI_F0006000_IRQ_0_PRIORITY -#define SPI_DW_PORT_1_REGS SNPS_DESIGNWARE_SPI_F0007000_BASE_ADDRESS -#define SPI_DW_PORT_1_IRQ SNPS_DESIGNWARE_SPI_F0007000_IRQ_0 -#define CONFIG_SPI_1_NAME SNPS_DESIGNWARE_SPI_F0007000_LABEL -#define CONFIG_SPI_1_IRQ_PRI SNPS_DESIGNWARE_SPI_F0007000_IRQ_0_PRIORITY +#define CONFIG_SPI_1_BASE_ADDRESS SNPS_DESIGNWARE_SPI_F0007000_BASE_ADDRESS +#define CONFIG_SPI_1_NAME SNPS_DESIGNWARE_SPI_F0007000_LABEL +#define CONFIG_SPI_1_IRQ SNPS_DESIGNWARE_SPI_F0007000_IRQ_0 +#define CONFIG_SPI_1_IRQ_PRI SNPS_DESIGNWARE_SPI_F0007000_IRQ_0_PRIORITY #define SPI_DW_IRQ_FLAGS 0 diff --git a/soc/x86/intel_quark/quark_d2000/Kconfig.defconfig.series b/soc/x86/intel_quark/quark_d2000/Kconfig.defconfig.series index 1f8a3bafcde..5428242ebc8 100644 --- a/soc/x86/intel_quark/quark_d2000/Kconfig.defconfig.series +++ b/soc/x86/intel_quark/quark_d2000/Kconfig.defconfig.series @@ -144,8 +144,6 @@ config SPI_DW_FIFO_DEPTH default 7 config SPI_0 def_bool y -config SPI_0_IRQ_PRI - default 0 endif # SPI if SOC_FLASH_QMSI diff --git a/soc/x86/intel_quark/quark_d2000/dts.fixup b/soc/x86/intel_quark/quark_d2000/dts.fixup index 1adf1947495..15e7cfad48f 100644 --- a/soc/x86/intel_quark/quark_d2000/dts.fixup +++ b/soc/x86/intel_quark/quark_d2000/dts.fixup @@ -33,3 +33,8 @@ #define CONFIG_ADC_0_BASE_ADDRESS INTEL_QUARK_D2000_ADC_B0004000_BASE_ADDRESS #define CONFIG_ADC_0_IRQ INTEL_QUARK_D2000_ADC_B0004000_IRQ_0 #define CONFIG_ADC_0_IRQ_FLAGS INTEL_QUARK_D2000_ADC_B0004000_IRQ_0_SENSE + +#define CONFIG_SPI_0_BASE_ADDRESS SNPS_DESIGNWARE_SPI_B0001000_BASE_ADDRESS +#define CONFIG_SPI_0_NAME SNPS_DESIGNWARE_SPI_B0001000_LABEL +#define CONFIG_SPI_0_IRQ SNPS_DESIGNWARE_SPI_B0001000_IRQ_0 +#define CONFIG_SPI_0_IRQ_PRI 0 diff --git a/soc/x86/intel_quark/quark_se/Kconfig.defconfig.series b/soc/x86/intel_quark/quark_se/Kconfig.defconfig.series index 730283815ac..8df70403ae7 100644 --- a/soc/x86/intel_quark/quark_se/Kconfig.defconfig.series +++ b/soc/x86/intel_quark/quark_se/Kconfig.defconfig.series @@ -118,15 +118,9 @@ config SPI_DW config SPI_0 def_bool y -config SPI_0_IRQ_PRI - default 2 - config SPI_1 def_bool y -config SPI_1_IRQ_PRI - default 2 - config SPI_DW_FIFO_DEPTH default 7 @@ -138,9 +132,6 @@ config SPI_2 config SPI_2_OP_MODES default 2 -config SPI_2_IRQ_PRI - default 2 - endif # SPI_SLAVE endif # SPI diff --git a/soc/x86/intel_quark/quark_se/dts.fixup b/soc/x86/intel_quark/quark_se/dts.fixup index a0ea3a1e248..3398937ced4 100644 --- a/soc/x86/intel_quark/quark_se/dts.fixup +++ b/soc/x86/intel_quark/quark_se/dts.fixup @@ -47,4 +47,19 @@ #define CONFIG_RTC_0_IRQ_PRI INTEL_QMSI_RTC_B0000400_IRQ_0_PRIORITY #define CONFIG_RTC_0_IRQ_FLAGS INTEL_QMSI_RTC_B0000400_IRQ_0_SENSE +#define CONFIG_SPI_0_BASE_ADDRESS SNPS_DESIGNWARE_SPI_B0001000_BASE_ADDRESS +#define CONFIG_SPI_0_NAME SNPS_DESIGNWARE_SPI_B0001000_LABEL +#define CONFIG_SPI_0_IRQ SNPS_DESIGNWARE_SPI_B0001000_IRQ_0 +#define CONFIG_SPI_0_IRQ_PRI SNPS_DESIGNWARE_SPI_B0001000_IRQ_0_PRIORITY + +#define CONFIG_SPI_1_BASE_ADDRESS SNPS_DESIGNWARE_SPI_B0001400_BASE_ADDRESS +#define CONFIG_SPI_1_NAME SNPS_DESIGNWARE_SPI_B0001400_LABEL +#define CONFIG_SPI_1_IRQ SNPS_DESIGNWARE_SPI_B0001400_IRQ_0 +#define CONFIG_SPI_1_IRQ_PRI SNPS_DESIGNWARE_SPI_B0001400_IRQ_0_PRIORITY + +#define CONFIG_SPI_2_BASE_ADDRESS SNPS_DESIGNWARE_SPI_B0001800_BASE_ADDRESS +#define CONFIG_SPI_2_NAME SNPS_DESIGNWARE_SPI_B0001800_LABEL +#define CONFIG_SPI_2_IRQ SNPS_DESIGNWARE_SPI_B0001800_IRQ_0 +#define CONFIG_SPI_2_IRQ_PRI SNPS_DESIGNWARE_SPI_B0001800_IRQ_0_PRIORITY + /* End of SoC Level DTS fixup file */